Under certain conditions, a false signal will be absorbed and a correct signal will be generated.
Current RHBD electronics are limited to speeds that approximate 250 MHz, regardless of the electronic process. The fact that determines the final speed is based on the nature of the current SEU (single-event upsets) radiation-tolerant latches, and the data flow between the latches through combinational logic.
The state-of-the-art RHBD technology has essentially ignored speed of operation because the speed afforded by the process was slower than the SEU particle impact and circuitry recovery time. In other words, a 1-ns SEU recovery time is within delay times associated with elements of the circuit design. As a result, designs could essentially “wait” for the particle effects to dissipate, and not suffer a large speed impact. However, a 1-ns delay greatly impacts the operating speeds of modern processes.
The current RHBD SEU-tolerant storage cell is achieved through redundancy, and there are a number of candidates used today (DICE, SERT). The basic operation of self-correcting logic (SCL) involves four signals that are passed between blocks. In a three-signal version, the latches require more transistors.
Clearly an SEU event can affect combinational logic as well as storage element modules. The output of either can momentarily be in error. Therefore, for self-correction, three or more signal representations are needed. Three or more combinational logic signals are passed between the SCL FF storage cells. The key design features for the SCL FF include the unusual capabilities to accept and respond to three inputs; to perform the majority vote function to insure the correct response; to not allow an SEU error to propagate; and to recover from a multiple clock SEU event and not enter a permanent error state. The SCL FF will essentially absorb a false signal if one of the three or four inputs is in error, and will output a correct set of signals. Correct signal levels are propagated to succeeding modules even while the SCL FF, or a combination logic block, is recovering from an SEU. Because it is not necessary to “wait” for the SEU event to dissipate, full advantage of the process speed is achieved.
This work was done by Sterling Whitaker and Gary Maki of the University of Idaho for Goddard Space Flight Center. GSC-16548-1