As semiconductor technology nodes scale down, the limitation on polysilicon pitch makes it almost impossible to shrink libraries built for previous technologies. To design a library for a new technology, all of the cells have to basically start from scratch. Starting over for each technology node shrink is time-consuming and expensive. Further, obtaining space qualification for a technology node will require significant time and money. If a RHBD (radiation-hardened-by-design) library gates invention shares the same transistor structured as the SASIC (Structured Application-Specific Integrated Circuit), it will benefit from the existing qualification effort and high-performance advanced technology of the SASIC design flow.
This innovative approach can provide a RHBD library independent of technology node. It can be transferred to a new technology with minimum effort. All gates in the library share the same transistor structure and therefore make it easier to be qualified for space applications. All gates in the library are based on one common cell. The layout for each gate is generated based on cell topology and connection of the basic cell.
This invention is technology-node-independent and easy to transition into architecture. The approach will not provide the layout directly; however, it includes the basic cell, metal connection for each library cell, and a script to build the layout for all library cells. Gate arrays built on a basic cell will provide PMOS and NMOS transistors. The metal connections within each cell in a standard library will be developed. An internal development script will use the basic cell metal connection and technology file to finish the layout of each cell.
This approach is a solution to polysilicon pitch issues that limit the implementation of advanced technology. For IBM 45- and 32-nm SOI (silicon-on-insulator), there are strict requirements for distance between polysilicon layers. Polysilicon pitch is aggressive at 190 or 380 nm. It is expected that the polysilicon pitch will aggressively trend more difficult in future technologies such as 28 and 22 nm.
This approach minimizes technology dependencies, thus making it easier to transition between technology nodes. Consequently, development time for new products is significantly shortened, and the uniform transistor structure enables high yield during manufacturing. The simple structure improves the ability to qualify radiation hardness since all of the silicon uses the gate array structure.
Prototype RHBD libraries for 45 and 32 nm SOI have been generated. These two libraries can be used for digital designs with standard ASIC flows, including space applications for which NASA will directly benefit. These libraries can replace and update existing RHBD library alternatives that are susceptible to single event upsets (SEUs).
This work was done by Xiaoyin Yao, Paul Eaton, and David Mavis of Microelectronics Research Development Corp. for Goddard Space Flight Center. GSC-16393-1