A charge-coupled-device (CCD) based high-speed imaging system, called a real-time, event-driven (RARE) camera, is undergoing development. This camera is capable of readout from multiple subwindows [also known as regions of interest (ROIs)] within the CCD field of view. Both the sizes and the locations of the ROIs can be controlled in real time and can be changed at the camera frame rate. The predecessor of this camera was described in "High-Frame-Rate CCD Camera Having Subwindow Capability"(NPO-30564) NASA Tech Briefs, Vol. 26, No. 12 (December 2002), page 26. The architecture of the prior camera requires tight coupling between camera control logic and an external host computer that provides commands for camera operation and processes pixels from the camera. This tight coupling limits the attainable frame rate and functionality of the camera.

The RARE Camera is a high-speed CCD-based imaging system that offers enhanced speed and functionality for tracking moving targets.

The design of the present camera loosens this coupling to increase the achievable frame rate and functionality. From a host computer perspective, the readout operation in the prior camera was defined on a per-line basis; in this camera, it is defined on a per-ROI basis. In addition, the camera includes internal timing circuitry. This combination of features enables real-time, event-driven operation for adaptive control of the camera. Hence, this camera is well suited for applications requiring autonomous control of multiple ROIs to track multiple targets moving throughout the CCD field of view. Additionally, by eliminating the need for control intervention by the host computer during the pixel readout, the present design reduces ROI-readout times to attain higher frame rates.

This camera (see figure) includes an imager card consisting of a commercial CCD imager and two signal-processor chips. The imager card converts transistor/transistor-logic (TTL)-level signals from a field programmable gate array (FPGA) controller card. These signals are transmitted to the imager card via a low-voltage differential signaling (LVDS) cable assembly. The FPGA controller card is connected to the host computer via a standard peripheral component interface (PCI). The host computer sends control parameters to the FPGA controller card and reads camera-status and pixel data from the FPGA controller card. Some of the operational parameters of the camera are programmable in hardware. Commands are loaded from the host computer into the FPGA controller card to define such parameters as the frame rate, integration time, and the size and location of an ROI.

There are two modes of operation: image capture and ROI readout. In image-capture mode, whole frames of pixels are repeatedly transferred from the image area to the storage area of the CCD, with timing defined by the frame rate and integration time registers loaded into the FPGA controller card. In ROI readout, the host computer sends commands to the FPGA controller specifying the size and location of an ROI in addition to the frame rate and integration time. The commands result in scrolling through unwanted lines and through unwanted pixels on lines until pixels in the ROI are reached. The host computer can adjust the sizes and locations of the ROIs within a frame period for dynamic control to changes in the image (e.g., for tracking targets).

This work was done by Steve Monacos, Angel Portillo, Gerardo Ortiz, James Alexander, Raymond Lam, and William Liu of Caltech for NASA's Jet Propulsion Laboratory.