ASIC for Reed-Solomon Coding and Related Functions

NASA's Jet Propulsion Laboratory, Pasadena, California

The Reed-Solomon downlink application-specific integrated circuit (RSDL ASIC) performs Reed-Solomon encoding of telemetry data, internally generates all timing and control signals necessary for the RS encoder, transfers frames of encoded data to a radio transmitter, and performs ancillary timing and control functions. The RSDL ASIC was designed for incorporation into a spacecraft downlink telemetry system, wherein the multiple functions involved in downlinking of telemetry transfer frames previously required interfaces with many discrete circuits and components. The RSDL ASIC may also be adaptable to terrestrial applications (e.g., recording in the entertainment industry) that involve Reed-Solomon encoding.

The RSDL ASIC (see figure) contains six distinct functional hardware/software blocks; an intersubassembly bus interface (ISB I/F), a timing-and-control block, a timing unit (not to be confused with the timing-and-control block), a bus arbiter, a Reed-Solomon (RS) encoder, and a synchronization-pattern block. All of these functional blocks are integrated in a highly efficient manner to fit on one chip. This ASIC operates in conjunction with a solid-state recorder interface unit (SSRIU), a static random-access memory (SRAM) that serves as an RS memory buffer, and a flight computer to forward telemetry transfer frames to the radio transmitter.

The RSDL ASIC Contains Six Hardware/Software Blocks that perform functions that previously required interfaces to many external circuits.

The timing-and-control block generates timing and control signals for the rest of the RSDL ASIC (including the timing unit) and keeps track of operational modes. Commands are carried out in the timing-and-control block, which then generates control signals for the synchronization-pattern block and the RS encoder to either shift the synchronization pattern, encode the message, or shift out the RS check bytes. The timing-and-control block also causes the timing unit to set or reset the spacecraft time and to generate the downlink rate used in the RS encoder. It swaps buffers and provides logic to force transfer frames to synchronize with a real-time-interrupt and use a specified downlink buffer thereafter. It captures the time when the first frame of the downlink buffer is sent out. It provides internal status and interrupt signals for software.

The synchronization-pattern block contains hard-wired logic circuitry that implements a standard synchronization pattern. It shifts data out serially to the RS encoder for every downlink frame, starting with the most significant bit.

The RS encoder block is based on the Berlekamp architecture and implements a standard (255, 233) RS code with an interleave depth of 5. In addition to the RS encoder, the RS encoder block includes a multiplexer to select input from either the synchronization-pattern block or the SSRIU. The RS encoder block is connected directly to the RS memory buffer.

The timing unit generates clock frequencies used throughout a command-and-data subsystem of the spacecraft. The timing unit includes a timing-chain section that converts the main clock signal into clock signals at most of the frequencies needed for that subsystem. From an oscillator with a frequency of 11,944,800 Hz, the timing chain generates a 64.005-Hz signal for the engineering flight computer, a 2,048.148 Hz signal used by a hardware command decoder, a pseudo-16385.185-Hz signal used within the timing unit, and a 32-Hz spacecraft clock signal. The pseudo-16385.185-Hz signal is used in conjunction with counters to generate the 32-Hz signal with high resolution in the following way: A 37-bit counter toggles the upper 32 bits of spacecraft time, giving resolution of 1/32 s. Another counter of 9 bits toggles a 14-bit subsecond time word.

The bus arbiter is the only unrelated block inside the RSDL ASIC. It contains circuitry to arbitrate the ISB between four possible bus masters.

The ISB I/F contains the logic circuitry that serves as an interface between the RSDL ASIC and an external bus arbiter or an engineering flight computer via the ISB. Software that resides in an external computer reads from and writes to internal registers in the ASIC via the ISB I/F. This block indicates whether data are stable and whether data written by the ASIC are captured correctly.

Notable features of the RSDL ASIC (in addition to those mentioned above) include the following:

It provides a spacecraft clock to keep track of time from 0 to 136 years in 61.03-ms intervals;
There is a correlation between spacecraft time and the first bit of a defined transfer frame;
It is easy to reconfigure the RSDL ASIC to other applications: The length of the transfer frame is programmable, software defines the time of the resynchronization of the transfer frames, and the RS encoder can be turned on and off; and
Software that resides in the flight computer can read and write status and interrupt signals generated by the RSDL ASIC.

This work was done by James A. Donaldson, Huy H. Luong, and Steven H. Wood of Caltech for NASA's Jet Propulsion Laboratory.For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com under the Electronic Systems category, or circle no. 180 on the TSP Order Card in this issue to receive a copy by mail ($5 charge).

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to