In the electronics industry today there are two commonly used high-speed memory types: static RAM (SRAM) and dynamic RAM (DRAM). Traditionally, SRAM embedded memory has been the designer's choice for fast memory, but since a typical SRAM bitcell is comprised of six transistors, that benefit comes at the expense of cost and silicon area. Embedded DRAM (eDRAM), whose smaller bitcell is comprised of a single transistor and single capacitor, offers a much lower cost option, but has higher latency and is typically used further from the processor. While DRAM is fundamental to electronic systems, it does have its limit — namely, its inability to scale to accommodate the migration to smaller, and therefore more advanced, process geometries. This limitation is further complicated by the fact that new application areas for memory are fast appearing, fueled by the popularity of digital home appliances and next-generation mobile devices, the digital convergence of electronic goods and telecommunications, and ever evolving media content.

DRAM Scaling Issue

Given its current roadmap, DRAM will soon reach its scaling limit due to the difficulty in shrinking its capacitor. Traditional SRAM will also face problems due to its instability at smaller process geometries. There is another alternative though — ultra-dense Zero- Capacitor DRAM (Z-RAM) memory technology. Z-RAM is a true single-transistor memory technology that harnesses the floating body effect of silicon on insulator (SOI) semiconductor devices. The elegance and simplicity of Z-RAM provides a number of significant advantages versus standard memory technologies:

  • Simplified manufacturing: Z-RAM does not require exotic processing steps for forming a DRAM capacitor, which lowers manufacturing costs and enables faster technology node introduction.
  • Smaller product size: Z-RAM is up to twice the density of DRAM and up to four times the density of SRAM, enabling more memory in the same area footprint.
  • Scalability: The Z-RAM bitcell is a transistor — the most scalable element of any semiconductor process — and has been demonstrated on advance device types such as FinFETs and MUGFETs.
Because Z-RAM is implemented on a standard SOI logic process, it will logically migrate into the same application areas that SOI does. This graphic depicts some of the high-performance SOI applications that will evolve in the coming years.

According to Jim Feldhan, president of Semico, "With wafer yields and die size reductions slowing down at each lithography generation, Z-RAM gives memory manufacturers a way to stay on the Moore's Law slope, and perhaps even accelerate it." In other words, Z-RAM is a memory technology that not only benefits today's memory manufacturers but, unlike DRAM, is well poised to address their future needs as well.

The Origins of Z-RAM

To fully understand the current and future impact of Z-RAM technology, it is helpful to first gain an understanding of how and why it was developed. Its origin traces back to the 1990s, when Dr. Pierre Fazan — now Innovative Silicon's chairman and CTO — was a senior fellow at Micron Technology. At the time, Dr. Fazan was working on the DRAM bitcell and had come to the conclusion that the complexity of fabricating the capacitor within the cell was going up exponentially with every new lithography process node. In the late 1990s, while working as a DRAM and eDRAM integration consultant, Dr. Fazan saw the same issues repeatedly at process nodes less than 90nm. Eventually, Dr. Fazan concluded that the DRAM cell would stop shrinking altogether. There was a clear opportunity for a new approach to the DRAM bitcell structure.

While at the Swiss Federal Institute of Technology (EPFL), Dr. Fazan managed a group of research scientists for work on projects in DRAM, Flash memory, and SOI technology. One of them, Dr. Serguei Okhonin, an expert in SOI technology, proposed the idea of a memory based on SOI transistors. This idea evolved naturally — the issues with scaling the capacitor within today's CMOS-based DRAM bitcell were well understood by the team, and the SOI transistor had a characteristic floating body effect (FBE) that could store a charge in the body of the SOI transistor, theoretically eliminating the increasingly complex capacitor altogether. In 2002, Innovative Silicon, Inc. was founded to develop and license this new concept.

From its very inception, Z-RAM was developed as the world's densest, and therefore lowest-cost, embedded memory technology for logic-based ICs such as mobile chipsets, microprocessors, networking, and other consumer applications. Today, thanks to an agreement by Hynix Semiconductor to license Z-RAM technology for use in its DRAM chips, the technology is now also being developed for standalone DRAM. The ability for Z-RAM to provide an elegant approach to manufacturing dense DRAMs on nanometer processes means that its technology can now cover all mainstream RAM-consuming markets, including standalone DRAM, microprocessors and other complex Systems-on-Chip (SoC).

But what exactly is Z-RAM technology? Put simply, Z-RAM is a single-transistor DRAM, consisting of just a single transistor as the memory bitcell. Unlike DRAM, which consists of a single transistor and a complicated capacitor, no capacitor or other structure is required to form a Z-RAM memory bitcell. Because it combines the state storage of the DRAM capacitor and the access function of the DRAM transistor together into a single transistor, the ZRAM memory cell is smaller, simpler to fabricate, and can be operated at higher performance than traditional DRAM cells.

A Closer Look

The simplicity of Z-RAM technology enables extremely dense memory, while providing excellent performance. In a conventional DRAM, the fundamental memory cell consists of a capacitor and a transistor. The capacitor stores the logic state '1' or '0', while the transistor enables the rest of the circuitry to access the capacitor. To read a DRAM memory cell, the transistor is turned on and the charge on the capacitor is allowed to flow onto a bitline, creating a small voltage which can then be detected. Because of the small geometries involved in DRAM fabrication, the capacitor can hold only a minimal charge and the resulting voltages that must be sensed are also very small. This means the circuits surrounding the memory cell are difficult to design, and they are sensitive to noise and voltage fluctuations (Fig.1).

In a Z-RAM memory cell the logic state is stored in the floating body of a transistor by using impact ionization to generate excess holes and a residual positive charge. Unlike the capacitor in a DRAM, a Read operation does not attempt to directly measure the quantity of charge present. Instead, the charge changes the gate threshold voltage on the order of 1 Volt which provides substantial read noise margin (Fig. 2).

There are other benefits as well, in comparison to traditional SRAM and DRAM solutions (see tables 1 and 2). Since Z-RAM utilizes a single-transistor as a memory bitcell, the scaling difficulties inherent in semiconductor design as process geometries shrink are minimized. Furthermore, Z-RAM does not require exotic process steps, nor does it require the fabrication of complex structures such as the capacitors needed for DRAM. Since capacitor fabrication is 20% - 30% of the cost of fabricating a stand-alone DRAM, this saving is substantial. As a result, the technology can smoothly transition with semiconductor process changes. The fact that ZRAM technology has already been successfully demonstrated on FinFETs and multi-gate devices at the bitcell — level meaning that experiments have shown these structures to both store and hold a charge with performance characteristics similar to a standard SOI-based ZRAM cell — makes it flexible for nearly any underlying transistor architecture changes.

Other compelling benefits of Z-RAM over traditional SRAM and DRAM are:

  • Cost Savings: Cost savings are proportional to the amount of real estate utilized. Since Z-RAM is 1.5× — 2× smaller than DRAMs, and 4× — 5× smaller than SRAMs, switching to Z-RAM provides designers with an enviable choice: include the same number of megabits of smaller, cheaper Z-RAM and therefore lower die cost, or keep die cost the same and include substantially more megabits of memory. Since Z-RAM can achieve random access times of under 2ns, Z-RAM is faster than DRAM and can be a direct replacement for SRAM in many applications.
  • Manufacturing Savings: Z-RAM uses no expensive capacitors or other structures that are complicated to manufacture, and often require substantial development effort to make yieldable in high volumes.
  • Lithography Friendly: Z-RAM features a logic-based, highly lithography-friendly layout. Its regular, grating-like structures are very amenable to reticle enhancement technologies. Additionally, the bitlines/words in the layout are straight which helps maintain high yields.
  • Minimal Standby Power: When the ZRAM array is not being used, all nodes in each memory cell are tied to ground. As a result there is very small array leakage — typically on the order of microwatts per megabit — and a nominal refresh current which is typically very small compared to 45nm and below SRAM array leakage. Consequently, Z-RAM can offer orders of magnitude lower standby power.
  • SOI Process: Z-RAM offers a compelling memory option for SoC and MPU applications built on an SOI process. For applications built on bulk silicon, there can be compelling reasons to convert to SOI. These include lower junction capacitance, speed/power advantages, a lower soft error rate, improved scalability, and the ease of closely coupling memory (both SRAM and Z-RAM) closer to logic. These benefits can quickly tilt the scale in favor of a transition to SOI.

Future Outlook for Z-RAM

With its wide array of features and benefits over existing technologies, ZRAM is ideal for use in today's standalone DRAM, SoC, microprocessor and portable consumer electronics applications requiring low power, high density, and high speed. In fact, its broad configurability in terms of speed, power, and density trade-offs enables it to be utilized almost anywhere high-speed memory is used, especially in high-performance SOI applications.

Table 1. Z-RAM versus embedded DRAM memory comparison table

Even though Z-RAM offers great value to today's memory manufacturers, its true potential will be realized in the coming years as DRAM's inability to scale becomes more problematic. For stand — alone DRAM, scaling may reach a roadblock below 30nm; for eDRAM, it's not clear if the industry can scale to 32nm and below. While the timeframe in which DRAM will hit its scaling limit is debatable, what is clear is that due to the ability of Z-RAM to scale it will be able to easily pick up where DRAM falls short — meeting the future needs of the most high-performance, as well as the most cost-sensitive, applications. In the embedded memory space this may mean a move into consumer electronic products, whereas in the stand-alone solutions space that may equate to any fast, low-power application currently handled by DRAM. Embedded SRAM will continue to be the memory of choice for smaller memories — register files, buffers, and other memories up to a megabit or two — but will generally be replaced by high-density eDRAM in the coming years.


Table 2. Z-RAM versus DRAM memory comparison table

While memory technologies like SRAM and DRAM have long dominated the electronics industry, the migration to ever smaller process geometries is driving the need for an alternate solution. That solution, both today and for the future, might well be Z-RAM memory technology. Its low cost and high performance enables it to act as a direct SRAM replacement in certain applications such as high density cache memories for microprocessors, game processors, and high-performance SOCs in general. Of course, Z-RAM is a high performance volatile memory, so it is not appropriate for applications where permanent storage is required. Even more important, thanks to its scalability, ZRAM is the only memory technology to date that is well positioned for use both as embedded and stand-alone memory in applications where DRAM has reached its scaling limit.

This article was written by Jeff Lewis, VP of marketing for Innovative Silicon, Inc. (Santa Clara, CA). For more information, contact Mr. Lewis at This email address is being protected from spambots. You need JavaScript enabled to view it., or click here .