Very-large-scale integrated (VLSI) circuits containing electronically reconfigurable arrays of transistors have been proposed as means to implement a forthcoming generation of a special class of digital/analog electronic circuits. The class in question is a subclass of advanced electronic and other equipment of a type called "evolvable hardware" (EHW). The major distinguishing feature of EHW is that under the direction of genetic and/or other evolutionary algorithms, its configuration and thus its functionality can be made to evolve until it exhibits a desired behavior or adapts to the environment in a prescribed way. An EHW system is said to be extrinsic if its evolution is directed and evaluated by a computer or other external system. An EHW system is said to be intrinsic if it includes an electronic or other subsystem that automatically directs and evaluates its evolution.

Transistors in Groups of n would be selectively connected to form VTs, which would be selectively connected into RTAs, and so forth up the hierarchy.

The evolution of an EHW system includes selective, repetitive reconfiguration of a set of available resources and/or the addition of building blocks. In the case of electronic EHW, such reconfiguration typically involves the connection or disconnection of transistors, amplifiers, inverters, and/or other circuit building blocks in an array of such building blocks. One example of electronic EHW is a programmable logic device (PLD), which contains logic-circuit building blocks. A pattern of interconnections among the building blocks can be downloaded to configure the PLD to perform desired logic functions. In some PLDs, the interconnection patterns are established by irreversible means; in most others, interconnection patterns can be changed reversibly by coupling appropriate signals to designated electronic (e.g., transistor) switches.

A VLSI circuit of the type proposed would be fabricated in complementary metal oxide/semiconductor (CMOS). It would contain hierarchical arrays and subarrays of transistors (see figure). Each subarray at the lowest level of the hierarchy would contain transistors Ti (i = 1 through n), each with a different combination of channel length and width (Li and Wi, respectively). The sources and gates of all n transistors in the subarray would be connected to a common source (S) and a common gate (G) line, respectively. The gate of the ith transistor could optionally be connected to a common drain (D) line via an analog transistor switch SWi by applying the corresponding control signal Ci.

Various combinations of electrical parameters would be associated with the various channel lengths and widths. Thus, one could choose one or more control signal(s) to connect one or more of the transistors Ti to make the subarray behave as though it were a single transistor [denoted a "virtual transistor" (VT)] with a desired analog or digital electrical behavior.

The VTs would be grouped into reconfigurable transistor arrays (RTAs), linked by inter-array buses. The RTAs could be similarly clustered on the chip with a bus connected to input/output (I/O) pins; alternatively, the hierarchy could be extended to one or more additional levels, ending in I/O pins at the highest level. The connections at the various levels of the hierarchy would be governed by a corresponding hierarchy of on/off control signals, ending in the previously mentioned control signals Ci at the lowest (transistor) level. With respect to a genetic algorithm for evolution of the overall configuration of circuitry on the VLSI chip, the portion of this hierarchy that ended at each transistor could be regarded as a chromosome fragment containing the genetic information for that transistor.

This work was done by Adrian Stoica of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp  under the Electronics & Computers category.

NPO-20078

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Reconfigurable arrays of Transistors for Evolvable Hardware

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    NASA Tech Briefs Magazine

    This article first appeared in the February, 2001 issue of NASA Tech Briefs Magazine (Vol. 25 No. 2).

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    Overview

    The document discusses a novel architecture for evolvable hardware (EHW) that enables reconfigurability at the transistor level, allowing programmable devices to adapt their functionality dynamically. This architecture is particularly significant as it extends the capabilities of current programmable devices, which primarily operate in the digital domain, to include analog and mixed-signal circuits.

    EHW refers to hardware systems that utilize evolutionary algorithms to modify their configuration and functionality over time. The proposed solution involves a reconfigurable transistor array composed of "virtual transistors" (VTs). Each VT consists of a group of transistors with varying parameters, such as channel width and length, which can be selectively connected via analog switches to form desired circuit configurations. This flexibility allows for the intrinsic evolution of circuits, where the system can automatically determine optimal configurations based on performance evaluations.

    The architecture is designed to be implemented in complementary metal oxide/semiconductor (CMOS) technology, which is widely used for both analog and digital circuits. The document emphasizes that the reconfiguration process can be viewed as a search for circuit behaviors that closely match required specifications. This search can occur either in software simulations or directly in hardware, enabling real-time adaptations.

    The document outlines the importance of having a variety of transistor parameters available for selection, as traditional fabrication processes fix these parameters. By allowing multiple transistors with different characteristics to be grouped together, the architecture can effectively create a virtual transistor that behaves as a single entity with desired electrical properties.

    The proposed architecture not only facilitates the evolution of circuits at the transistor level but also blurs the lines between analog and digital systems. It allows for the specification of both circuit topology and individual transistor parameters, enhancing the adaptability and performance of hardware systems.

    In summary, this document presents a groundbreaking approach to EHW that leverages reconfigurable transistor arrays to achieve a high degree of flexibility and adaptability in circuit design, paving the way for advanced applications in various fields, including aerospace, telecommunications, and beyond. The work was conducted at the Jet Propulsion Laboratory under NASA's auspices, highlighting its significance in the context of cutting-edge technology development.