The design of a highly reliable controller for a digital data bus incorporates improvements, in both hardware and software, over the basic design of a low-speed, low-power, serial bus known in the industry as "I2C." ("I2C" signifies "inter integrated circuit bus" — a bus developed by Philips Semiconductors in the early 1980s.) The original design of the I2C bus lacks fault-tolerant features that could protect against bit errors, shorting of output drives, or babbling nodes (nodes that misbehave or disrupt normal communication). The present design adds such features: It augments the standard I2C bus protocol with low-overhead error-detection features and a fail-silent messaging system, and it adds hardware features that automatically isolate babbling nodes. These fault-tolerant features can be disabled through software (for example, to aid testing), but the design makes it difficult to do this accidentally.

  • The principal advantages of the present design over prior I2C-bus designs are the following:
  • Cyclic redundancy checking (CRC) is used to obtain partial immunity to errors in messages on the bus.
  • Devices on the bus are inhibited from monopolizing the bus, even when hardware or software faults occur.
  • Special commands have been added to enable direct control of one node by another
  • Asynchronous logic in the basic design has been replaced with synchronous logic.

In addition, the bus is compatible with devices that have been designed to function on previously designed, standard versions of the I2C bus.

The overall function of a controller according to the present design is that of an interface between a peripheral component interface (PCI) bus and an I2C bus. The design calls for some basic I2C bus-controller components and associated logic circuitry for a (PCI) port, plus application-specific integrated circuits (ASICs) that implement logic functions to manage the flow of messages and to exert digital input/output (DIO) control. Additional logic circuits are used as watchdog timers and to effect CRC. On each DIO ASIC, there are two I2C bus controllers that drive separate system and subsystem busses. Within each I2C bus controller, there are two I2C commercial-off-the-shelf I2C cores. A transmitting line and a clock line between the cores are ANDed together to make them share a common clock and a data-transmission driver with a separate mixed-signal ASIC.

This work was done by Ryan Fukuhara, Huy Luong, Robert Rasmussen, Savio Chau, and Leonard Day of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at  under the Electronic Components and Systems category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

Intellectual Property group
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109
(818) 354-2240

Refer to NPO-20876, volume and number of this NASA Tech Briefs issue, and the page number.

This Brief includes a Technical Support Package (TSP).
Document cover
Design of a highly reliable controller for an I2C bus

(reference NPO-20876) is currently available for download from the TSP library.

Don't have an account? Sign up here.