Tech Briefs

FPGAs can be reconfigured to provide higher capacity or fault-tolerant redundancy.

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA.

This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

For fault tolerance, it is assumed that only one fault will occur within a voting group within one voting cycle, and thus, the fault can be eliminated by majority voting. Three voters are often used, providing three values to the next voting group, and so on, with the entire device triplicated. The only connection between the three sections of the device is the voters. By changing the operation of the voters, the sections can operate independently. A system of triple-redundant voted configuration data (if needed, according to the configuration memory type) can be used to provide routing connections to allow communication between the sections. The ability to use hardware-based redundancy where needed in high-capacity applications may help avoid high development costs, difficult maintenance, and complex failure of firmware redundancy schemes.

This work was done by Robert Shuler, Jr. of Johnson Space Center. For more information, download the Technical Support Package (free white paper) at under the Electronics/Computers category.

This invention is owned by NASA, and a patent application has been filed. Inquiries concerning nonexclusive or exclusive license for its commercial development should be addressed to the Patent Counsel, Johnson Space Center, (281) 483-1003. Refer to MSC-24464-1.

This Brief includes a Technical Support Package (TSP).

Reconfigurable Fault Tolerance for FPGAs (reference MSC-24464-1) is currently available for download from the TSP library.

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