High-Density Rad-Hard Reconfigurable FPGA

Xilinx, Inc. (San Jose, CA) has launched the industry’s first high-density, rad-hard reconfigurable FPGA. The new devices are built on the second-generation ASMBL™ column-based architecture of the Virtex-5 family with support in Xilinx’s ISE® Design Suite. Virtex-5QV devices integrate many of the same hard-IP system level blocks, such as flexible 36-Kbit/18-Kbit block RAM/FIFOs, second generation 25x18 DSP slices, power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, and PCI Express™ compliant integrated Endpoint blocks. The Virtex-5QV device offers 130,000 logic cells, 320 DSP Slices supporting fixed and floating point operations, and 836 user I/Os programmable to more than 30 different standards for applications and ease of interfacing to a wide variety of system components. The Virtex-5QV family also provides the industry’s first integrated high-speed connectivity solution for space with 18 channels of 3Gbps Multi-gigabit Serial Transceivers for chip-to-chip, board-to-board and box-to-box communication.

The rad-hard features inherent in Virtex-5QV devices are backed by the highest levels of in-beam testing by the Xilinx Radiation Test Consortium (XRTC) and equivalent to millions of device years in space radiation environments. This means Virtex-5QV FPGAs provide exceptional protection against Single-Event-Upset (SEU), Total Immunity to Single-Event Latchup (SEL), high tolerance to Total Ionizing Dose (TID), as well as data path protection from Single-Event Transients (SET).

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