Transitioning to OpenVPX for Next-Generation C4ISR Systems

VPX systems offer tremendous performance for the Mil/Aero market, including naval, airborne, and ground-based computing systems. The architecture provides an unprecedented combination of bandwidth, user IO, and rugged design, in both a 3U and 6U Eurocard format. The new OpenVPX initiative has opened up new definitions for VPX system interoperability, including defined module profiles, slot profiles, backplane & chassis configurations, secondary expansion fabrics and control planes, and higher speed fabric options.

Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR)

C4ISR embedded computing systems have certain general needs, both today and continuing into the future. These include:

Mission-critical reliability — For Mil/Aero applications, system failures can cost lives.
Higher bandwidth — Weapon and intelligence gathering platforms are using more intensive digital signal processing for gathering, relaying, and processing data.
Rugged design — Platforms need to survive the shock, vibration, and effects in aircraft, ground, and sea based applications.
Stable architecture, less risk — Platforms need to last many years, even decades. Vendor support is also critical.
Performance density — As space restrictions get tighter, the system needs options for small form factors while retaining high performance.

Figure 1. Figure 1a shows a standard 6U 5-slot VPX backplane and 1b shows a simple side-view diagram of how the J0-J6 connectors are used.

VPX, and later OpenVPX, were collaboratively created within VITA (VME International Trade Association) by dozens of experts in the military/aerospace community. Based on the rugged Eurocard format like VME and CompactPCI, VPX comes in both 3U and 6U standard board sizes with typically 1.0" pitch (0.80" and 1.2" pitch are also possible). VPX uses a high-speed Multi-Gig connector and offers plenty of IO in a rugged, open standard architecture. With dozens of vendors and some backwards compatibility options to VME, the architecture is stable and will be supported for years to come.

OpenVPX for System Interoperability

Figure 2. A Slot Profile of an OpenVPX (VITA 65 compliant) version of the 6U 5-slot backplane. The profile provides more details on the data signals, utility plane, and more.

If there is any fault with VPX, it was made to be very flexible. This flexibility was beneficial for customized solutions, particularly for how high-speed IO is transported throughout the system. However, it was difficult, if not impossible, to be assured that a board from one vendor would work with one from another vendor, along with a backplane from yet another party. Therefore, the OpenVPX initiative commenced in early 2009 with a goal of providing interoperability definitions for the VPX specification. The initiative was rolled into VITA as the VITA 65 specification, which was approved by ANSI in June 2010.

In short, OpenVPX provides definitions for backplane configurations, which are comprised of slot profiles into which various module profiles can be plugged. The module and slot profiles ensure that a vendor’s VPX boards (modules) have pinouts that are interoperable within the VPX backplane slots. The backplane configuration tells the user which slot profiles are utilized, including information on the data rate, routing topology, and fabric used.

When it comes to backplane functionality, there is very little change. The new standard simply redefined two reserved P0/J0 signals Aux_Clk (+/-) and added one P1/J1 single ended Utility signal of Maskable Reset and redefined the Res_Bus signal to GDiscrete. The Aux_Clk and GDiscrete pins were already bussed anyway, so the change is minimal. Also, the SysCon signal is now configurable.

Let’s take a look at a standard 6U VPX 5-slot Mesh backplane and compare it to an OpenVPX version. Figure 1a shows a 6U 5-slot VPX backplane and 1b shows a sideview of how the J0-J6 connectors are used.

The standard VPX version has pinout charts for P0 and P1 sections with the P2-P6 as “undefined”. Although the P0 and P1 sections have defined pinouts, there are no details in VPX as to the kind of signals such as thin pipes, fat pipes, or ultra thin pipes. Also, the details of the utility plane are not as clear.

In the OpenVPX version of the same backplane, Figure 2 shows the payload slot profile. It provides more information for the data plane section (in yellow), which in this case defines 4 fat pipe lanes. Also, the utility plane sections are clearer. Although this backplane does not have a control plane, if it had one we’d also see this in the payload slot profile, along with the type of signal (thin pipes are commonly used for the control plane).

Figure 3. The Backplane Profile Chart tells us which OpenVPX Slot Profile(s) is used, the pitch, and data rate of the backplane.

The Slot Profile that is referenced in Figure 2 gives us some details on the card plugging into the slot. For example, the slot profile number SLT6 says it’s a 6U slot profile (a 6U board), the PER says it’s a peripheral slot, 4F means it has 4 fat pipes and the 10.3.1 is where you can find details on this slot profile in the VITA 65 specification. For OpenVPX, fat pipes have 4 links (4 Tx pairs + 4 Rx pairs), thin pipes have 2 links, and ultra thin pipes have one link. The wider bands, like fat pipes, are typically used in the data plane, while the control plane will often have the thin pipe or ultra thin-pipe signals. Slot types are comprised of peripheral slots, payload slots, switch slots, or bridge slots.

The backplane profile of the backplane also provides more information. For example, this 6U 5-slot’s profile is BKP6-DIS05-11.2.16-1. The BKP6 tells us it’s a 6U backplane profile. DIS05 means it’s a distributed (like a mesh or ring) architecture and has 5 slots. The 11.2.16 is the section of the specification where you can find details on this backplane profile. The “-1” tells us the data rate is 3.125 Gbps (-2 means 5 Gbps and -3 means 6.250 Gbps).

The backplane profile chart in Figure 3 shows the profile name, the pitch, the corresponding slot profile for the backplane, the control plane data rate (if applicable) and the data rate of the backplane.

The slot type (like DIS05) section of the profile name is an important part of the description. The main fabric topologies are CEN for centralized, DIS for distributed, and HYB for hybrid. “Centralized” means it has a centralized switch slot and the routing could be similar to a Star topology. The DIS and CEN configurations typically have payload and switch slot types. The HYB will typically also define peripheral, bridge, and bus slot types like “VME” to account for connections to the legacy bus slots. The bridge slot does not mean an active bridge board (like a cPCI Bridge) is being used. Rather, it just refers to the fact that this VPX slot also has pinouts defined for the parallel bus (like VME).

Future Designs for VPX/OpenVPX

There are some interesting configurations coming up in OpenVPX. They include special connections for optical connectors and another version for a RF connector interface. VITA 67 is underway to add RF connectors to the OpenVPX backplanes. Figure 4 shows the new gold connectors on a backplane.

Another very compelling new solution for VPX is cabling systems. Compliant to the latest VITA 46 specifications, the cabling system can be used for IO to bulkhead connectors, slot-to-slot connections, and out-of-band communication. The cabling system can also be used for system development. Figure 4 also shows an example of these cables plugged into a VPX backplane. The direct cabling system also has front-plug versions, which allow testing across the backplane or full interconnect path. The metal shroud can be used in deployable systems to securely hold the cables in place and satisfy MIL-STD-810E and 901D for shock and vibration.

Figure 4. This photo shows two upcoming solu- tions in one. The gold connectors are for RF sig- nals per the VITA 67 specification underway. Also shown is a VPX cabling solution with a shroud to secure the cables that clip into the backplane.

There are several reasons to use a cabling system in a deployed VPX platform. Many applications such as ATRs (air transport racks), may not have RTM (rear transition module) options. In some cases, the signal speeds through the RTM are not enough. In other designs, the system cannot afford to lose a slot of space to an IO slot. The VPX cabling system provides a rugged and robust alternative with a high-speed connection that is plugged directly into the MultiGig connector in single or multi-wafer formats.

OpenVPX provides definitions for VPX backplanes, modules, and chassis to ensure that the products are interoperable. The backplane configurations have been defined to show the collection of slot profiles it entails, including information on the data rate, routing topology, and fabric used. Exciting VPX/OpenVPX products have emerged that offer the performance solutions required in C4ISR systems.

This article was written by Melissa Heckman, Electrical Engineeer, Elma Bustronic Corporation (Fremont, CA). For more information, contact Ms. Heckman at This email address is being protected from spambots. You need JavaScript enabled to view it., or visit http://info.hotims.com/28057-451 .