This graphic depicts the process for identifying transistors that can be slowed down in order to reduce wasted energy while maintaining performance. (Tela Innovations)
A University of California, San Diego technology that significantly reduces the amount of energy wasted by chips in electronic devices has recently passed the trillion watt-hour milestone in energy savings, according to the technology’s current licensee, Tela Innovations.

Electronics are constantly leaking power, and that energy is wasted without having contributed anything to performance. This is especially true of devices that consumers tend to leave turned on even when they aren’t being used. With residential energy costs at just over 11 cents per kilowatt hour, the savings of this technology are significant and growing, so far totaling over $100 million.

The technology, co-invented in 2003 by UC San Diego Jacobs School of Engineering Professor Andrew B. Kahng and his then-student Puneet Gupta, subtly modifies the dimensions of transistors, the tiny switches that control the flow of electricity in an integrated circuit. This approach, known as gate-length biasing, exploits the fact that slower transistors leak less power. The invention essentially ensures that transistors on a chip are as slow as possible without affecting performance.

The technology is now widely used in numerous applications such as network processors, Internet routers, and the graphics processing units (GPUs) that are found in personal computers, tablets, and game consoles.


Kahng and Gupta solved a complex optimization problem to identify which transistors can be slowed down. And they had to do this without changing the way chip designs are handed off from design teams to the silicon foundries that manufacture the chips.

“The key is figuring out which of the hundreds of millions of transistors on the chip to modify,” said Kahng. “Many, but not all, of the transistors can be made slower without affecting the clock frequency. We developed a tool to maximize leakage power savings without affecting product performance, and we created a flow to make this transparent and easy for both designers and manufacturers.”

“As transistor dimensions continue to shrink in advanced manufacturing technologies, the potential for wasted energy only increases,” Gupta added, “By adding even a few nanometers to the channel length of a transistor – using gate-length biasing – the invention substantially reduces leakage power while only slightly slowing down the transistor’s switching speed.”

(University of California, San Diego)