The production of many electronic devices begins with wafer processing. In addition to complementary metal oxide semiconductor (CMOS) integrated circuits (ICs), this can include such diverse devices as radio frequency (RF) components based on III-V compounds and chemical detectors based on carbon nanotube (CNT) field effect transistors (FETs). In both R&D and production applications, there is a great deal of effort devoted to increasing device test throughput in order to shorten the time to market and reduce costs.

Figure 1. Comparison of elapsed times between sequential and parallel testing of four DUTs. The sequential test time (ts) is approximately 3.8 times longer than the parallel test time (tp).

One way of doing this is to run tests in parallel on wafer test elements (as opposed to testing devices sequentially) using automated or semi-automated wafer probers connected to parametric test systems. This reduces overhead time and increases throughput by using instruments that might otherwise sit idle, waiting for a test routine to call them into action.

Parallel Test Process

The shortest, simplest definition of parallel parametric test is that it’s an emerging strategy for wafer-level parametric testing that involves concurrent execution of multiple tests on multiple scribe line test structures. It offers a relatively inexpensive way to increase throughput, thereby lowering the cost of ownership (COO) significantly. Just as important, parallel testing can address the growing need to perform more tests on the same structures in less time as device scaling increases the randomness of failures.

In most cases, the structures being tested in parallel are in a single Test Element Group (TEG) located in a wafer scribe line. Even among leading edge manufacturers, very few have progressed to the point of testing structures in different TEGs simultaneously. Implementing this strategy involves using the tester’s controller to interleave execution of the multiple tests in a way that maximizes the use of processing time and test instrumentation capacity that would otherwise be standing idle. When the design of test structures allows, this “multi-threaded” approach to test sequencing reduces the execution time for multiple tests on multiple structures to little more than the time needed to execute the longest test in the sequence.

To illustrate the throughput advantage that parallel testing offers, it is helpful to contrast it with the traditional sequential approach to parametric test (Figure 1). The total test time for an individual TEG is approximately the sum of the test times for the individual test devices, plus any delays due to switching latencies, which can be significant.

Ideally, parallel tests start simultaneously and chain together with no delays in each thread, but realistically, there are slight delays between the start times of each test sequence due to latencies in the prober, controller, and parametric tester. In sequential mode, tests run consecutively, synchronized so that the start of the next test sequence begins upon the conclusion of the prior sequence.

Figure 2a. Schematic of sequential mode testing.
Figure 2b. Schematic of parallel mode testing.

Today’s parametric test systems can be equipped with up to eight Source-Measure Units (SMUs), although most systems have fewer installed. Nevertheless, consider a tester equipped with eight SMUs operating in sequential mode for simple tests such as measuring a resistor, which requires one SMU for the two nodes. In this case, seven SMUs would be sitting idle. Parallel testing increases utilization of the test cell and boosts throughput by using available tester resources to measure multiple devices simultaneously.

Devices tested in parallel may be all the same type (homogenous) or different types (heterogeneous). For example, two transistors, one resistor, and one diode could potentially be measured independently in parallel by performing different connect-force-measure sequences on all four devices simultaneously. Figures 2a and 2b illustrate the difference between sequential mode and parallel mode testing within a TEG.

Figure 2 illustrates how the parallel mode test sequence maximizes use of available instrument resources (SMUs, signal generators, etc.). Parallel test has the potential for greatly reducing test times or allowing the collection of more data within a given time frame.

Note that we are discussing only parallel testing at the wafer level, not of packaged devices. Although both types of parallel testing use a similar testing strategy (i.e., the use of multiple SMUs operating asynchronously to reduce total test time), there are obvious differences. The most significant one, other than the size and cost of the test hardware itself, is that functional tests of packaged devices are largely immune to the parasitic capacitances between wafer devices under test that can interfere with parametric test accuracy, whether tests are performed sequentially or in parallel.

Parallel Test Strategies

For mature wafer processes and test cells, the most practical way to get involved in parallel testing is to start with existing TEGs and change the test sequencing (Figure 2). Typically, this would require analysis of both the TEG and the test sequence to identify opportunities for reordering or regrouping existing tests on heterogeneous structures in a way that minimizes the time needed for switching between test pads. This represents the fastest, surest way to achieve significant throughput improvements with a relatively limited investment in analysis effort, new software, and test sequence modifications.

There may be cases where a more extensive overhaul of the test process is justified to achieve larger gains in test throughput. This demands much more extensive analysis of both the test sequence and the TEG itself, because it requires significant changes to both. Typically, this also requires a number of new reticles that must be designed, created, and validated to allow parallel testing of more structures within the TEG. This strategy may also require changes to the probe card design, as well as the installation of additional source-measure instrumentation. The expense and time required for these changes must be weighed against the expected cost reductions and benefits from more extensive data collection.

During technology development for new products, it’s relatively inexpensive to design new TEGs in a way that maximizes the number of structures that can be tested in parallel. Given that there are no existing reticles or test sequences that must be replaced, there’s no existing testing process to disrupt. While this offers the highest potential for payback in terms of throughput, it’s wiser not to try implementing parallel test for the first time on a new product, when there are many other priorities to consider while trying to ramp up production. Instead, the knowledge gained from first implementing parallel test on mature processes can be applied to the process of implementing it on new products later. Parametric test vendors can also provide enormous assistance by reviewing test structures and algorithms, which may make it possible to ramp parallel test technology significantly faster.

Parallel Test Advantages and Benefits

The most obvious advantage of parallel test is its impact on the parametric tester’s COO. The largest “lever” on COO for a process or metrology tool is system throughput. Since parallel test can increase throughput dramatically, it has a proportional effect in driving down COO. Users have documented throughput increases due to parallel test by factors ranging from 1.05X to 3.9X. The degree of throughput improvement that a particular test cell can achieve depends on a variety of factors, which include:

  • Existing test structure and pad layout. In order to minimize precious wafer real estate devoted to TEGs, test structures typically have been designed with shared gate pads, which can make it impossible to test certain structures in parallel.
  • Specific combination of test structures within the TEG. Consider, for example, a test structure made up of an array of transistors, all with a single shared gate pad. Complete characterization of these devices in parallel testing would be impossible with such a structure. Conversely, a resistor network would likely allow testing of all the resistors in parallel because such a structure would have a pad at every node in the network, allowing the tester to source current across the network, then measure voltage drop at each node.