Have you attended an electronics or design tradeshow lately? Have you visited a big-box retailer or browsed an online electronics vendor? If so, you’ve probably seen many examples of wearable technology, including smart glasses, clothing, wristwear, footwear, neckwear, and headbands. Wearable computing is one of the hottest consumer electronics trends on the market, with global sales expected to grow from $14 billion in 2014 to over $70 billion in 2024, according to IDTechEx.

Packing five ESD diodes in a 0402-size flip-chip package, the SP1012 Series TVS Diode Array provides five times the diodes in a package less than a square millimeter in size, helping circuit designers economize on both PCB space and costs.
As consumers become increasingly dependent on wearables like smart glasses and fitness wristbands, circuit designers are tasked with incorporating advanced circuit protection technologies that safeguard the device as well as the user. Without proper protection, the device’s sensor circuits, battery charging interfaces, buttons, or data I/Os could be irreparably damaged by electrostatic discharge (ESD) that is often caused by close interaction with the user.

Circuit designers face many challenges in the design process stemming from the shrinking form factor of most wearables and the demand for improved device performance. The answers to the 15 questions asked here will help today’s circuit designers improve the performance, safety, and reliability of their wearable technology designs.

1. What is the benchmark for size versus ESD robustness?

In the past, large diode structures were needed to achieve excellent ESD performance (low clamping voltage). Since wafer fabrication processes and back-end assembly capabilities have steadily improved, it is now possible to have very robust ESD protection in small form factors. For example, the general-purpose 01005 transient voltage suppression (TVS) diode can withstand 30kV contact discharge (IEC 61000-4-2). It also has a dynamic resistance value of less than 1Ω.

2. How much area shrinkage can be achieved with the latest technology in ESD?

The most common discrete form factor for TVS diodes is the SOD882 package, which is equivalent to an outline of 1.0 × 0.6 mm. Moving to the 0201 form factor (0.6 × 0.3 mm) allows the designer to save approximately 70 percent in board area.

3. What are the downsides of a small form factor?

Per the advancements discussed in the first question, we are not seeing any downsides related to ESD performance. Discrete semiconductors with a small form factor can have the same level of ESD robustness (30kV) and low clamping performance (dynamic resistance <1Ω) as their larger counterparts (e.g., SOD323, SOD123). However, the small size of the component may present manufacturing challenges. At 0.4 × 0.2 mm, the 01005 package will require well-designed board treatments (solder pads, stencil thickness, etc.) to ensure that the component does not slide or “tombstone” during the reflow solder process.

4. If I have discrete TVS diodes on each of the pins of the integrated circuit (IC), will they occupy more of the board area and also cause the bill of material (BOM) to increase?

SP3022 Series Low Capacitance ESD Protection TVS Diode Arrays provide symmetrical protection for high-speed data lines when AC signals are present. They are also well suited for consumer electronics like fitness bands, smart watches, smartphones, tablets, and eReaders.
In general, most designs do not require board-level TVS diodes at each of the IC's pins. Instead, the designer should determine which pins have exposure to the outside of the application. Typical circuits include USB, audio, button/switch control, and other data buses. Since adding these discrete devices will take up board space, it’s important to concentrate on reducing their size. For some applications, there are some space-saving multi-channel arrays available.

5. When IC designers create products that employ lower working voltages, can the end application (e.g., smartphone or tablet) still be reliable?

ESD protection device manufacturers continue to work to develop products with ever-lower clamping voltages. They also work with board-level designers to ensure that proper circuit layout practices are followed to protect the reliability of the application. Coupling products with low dynamic resistance and proper board layout practices will ensure that applications with even the most sensitive IC will still perform reliably.

6. How do I choose between unidirectional or bidirectional TVS diodes?

Unidirectional diodes are typically used for DC circuits, including pushbuttons and switches. They are also designed for use in digital circuits where there is no negative voltage as part of the signal (e.g., USB, HDMI, etc.). Bidirectional diodes are used in AC circuits, which may include any signal with a negative component greater than -0.7V. Examples of these circuits include audio, analog video, legacy data ports (e.g., CAN, LIN, RS-485, etc.) and RF interfaces (e.g., cellular, Bluetooth, NFC, etc.).

7. To protect the IC’s pins with a TVS diode, what are the key considerations for trace?

Unlike lightning transients, ESD does not unleash a large amount of current for a long duration. Instead, it is important to move the ESD charge from the protected circuit to the ESD reference in a very short amount of time (<200 ns). The length of the trace (from the I/O line to the ESD component; from the ESD component to ground), not the width of the trace to the ground, is the overriding factor. This length should be kept as short as possible to limit parasitic inductance. Because of this, recent package developments include μDFN outlines that fit directly over the data lanes to eliminate the need for stub traces.

8. The length of the ground path influences the parasitic inductance, while the width influences the parasitic capacitance. In terms of form factor, how do I avoid ESD disruptive discharge?

The inductance will act as a choke for the ESD transient and degrade the protection performance. The parasitic capacitance will degrade high-speed signal performance. Designers should not only minimize the length/width of the stub trace, but also attempt to eliminate it. For the connection to the data or signal line, place the solder pad right on or adjacent to the trace, if possible. This can be done for discrete diodes as well as a number of arrays that are designed to be placed right over the data tracks. This underscores the need to consider the board-level ESD protection approach as early as possible in the design process.