The ongoing challenge for today’s semiconductor test engineers is to identify and create new test solutions that can offer significantly lower test costs as well as address the need for configurable, open-architecture, flexible test solutions that can provide comparable features to proprietary ATE platforms. In particular, for test requirements with low to moderate volumes — such as pilot production, verification, and focused production test applications — the need for flexible and cost-effective ATE solutions is particularly acute. For these applications, test engineers historically have relied upon legacy test systems that have a low acquisition cost, but high operating costs or in-house designed rack-and-stack solutions. However, semiconductor test system solutions based on the PXI platform have made significant advancements in functionality and performance over the past three or four years, offering test engineers a viable alternative for both current and future test needs.

Figure 1. System configuration with PMU, digital instrument, and switching matrix.
For digital and system-on-chip test applications, today’s PXI test systems offer moderate to high digital channel count capability with parametric measurement unit (PMU) per pin functionality. However, existing PXI digital subsystems have been largely limited to verifying DC and functional test characteristics of a device due to their limited timing engine capabilities. To fully meet the test requirements found in “big ATE,” a PXI-based test system (and its digital subsystem) must also be capable of testing a device’s AC characteristics such as setup and hold times — a capability that has not been easily achieved by the current generation of PXI instruments. The latest generation of PXI systems and instrumentation offers many of the features found in proprietary ATE systems, including an advanced timing engine and software tools for importing test vectors and developing test programs.

Semiconductor Test Requirements

The basic test needs for digital and mixed-signal devices include DC/AC parametric and functional tests. For the DC tests, all of a device’s pins must be characterized, which requires a PMU. A PMU, which can source voltage/measure current or source current/measure voltage, must be able to access all of the device’s pins, which requires some type of switching/multiplexer if a single PMU is used. Once DC characterization is completed, functional/AC parametric testing of the device can be performed. In this case, a digital instrument with sufficiently deep memory, per-channel programmability (voltage, loads, and direction), programmable edge placement, and real-time compare provides the key features for testing AC parametrics and functionality. A basic setup that addresses these capabilities is shown in Figure 1.

Figure 2. 3U PXI, 32-channel digital I/O with per-pin PMU architecture.
The configuration shown is not practical for even moderate pin-count ATE systems. Today’s PXI test systems incorporate a PMU per-pin or channel architecture, offering high channel count configurations and superior test performance (both for speed and measurement accuracy). Figure 2 details the architecture of a digital instrument that includes a PMU per-pin configuration. PXI test systems offer a high-channel-count digital and mixed-signal test system in a small, compact, single PXI chassis.

Performing DC Parametric Tests

As noted, a PMU can be used in one of two modes to perform DC characterization tests on the input and output pins of digital devices:

  • Force voltage and measure current. With this method, the PMU applies a constant voltage, and using its onboard measurement capability, it measures the current being drawn by the device/pin being tested. The voltage being supplied by the PMU can also be measured.
  • Force current and measure voltage. With this method, the parametric measurement unit either forces a constant current across a device, or sinks a constant current from a device pin and then measures the resultant voltage. The PMU sink/source current also can be measured.

By combining a PMU per channel with digital test capabilities in one instrument, performing a range of DC tests on digital and mixed signal devices is significantly simplified. Common DC tests performed on digital devices include input voltage levels (VIH/VIL), output voltage levels (VOL/VOH), input leakage, and output short circuit current tests.

Performing Input Leakage Test and V-I Tests

Figure 3. Input leakage test using the digital instrument’s PMU capability.
Testing a device’s inputs includes leakage current testing as well as characterizing the protection diodes present on each input of the device under test (DUT). These tests are performed by applying a constant voltage in steps over a specified test voltage range to the DUT input pin and measuring the input current at each step (Figure 3). As leakage currents are often in the uA range, the PMU should be set to its more sensitive current ranges to achieve more accurate measurements.

To perform an input leakage test, the DUT is powered up and the PMU pin is set to Force Voltage/Measure Current Mode. At each input voltage setting, the PMU measures the current being drawn by the input and then verifies the value against the DUT specification. The actual test voltage that the PMU is sourcing can be measured as well. The testing technique can also be used for VIL and VIH testing.

For measuring/characterizing the input protection diodes connected to the device’s ground and VCC pins, the PMU is configured for force voltage/measure current with the voltage stepped in small increments in order to produce V-I curve for each diode. The device begins to conduct at a junction voltage of about 0.7 volts.

AC Parametric Test Capabilities

To adequately address the capabilities and functionality found in proprietary big iron ATE digital instrumentation, today’s PXI-based digital subsystem must have flexible and dynamic timing per-pin or channel capability. Unlike existing 3U PXI digital subsystems that employ a “singular” timing system in which all I/O channels are clocked with the same clock edge, a dynamic timing per-pin system provides the flexibility to position data independently and dynamically on a perchannel basis. Additionally, data formatting (e.g. non return to zero or return to zero, etc.) offers added flexibility when emulating complex bus timing, or if testing for pulse width sensitivity. With these dynamic timing features and data formatting, a PXI-based test system can offer the test capabilities that are comparable to big iron ATE systems.

Dynamic timing implies the ability to move edges anywhere within a test step with adequate resolution. The challenge for a singular timing system is that edge placement will be limited to a rising or falling edge of the vector clock rate, and edge placement will be fixed for a complete vector burst. For example, if the vector clock rate is 100 MHz, edge placement will be limited to 5 ns resolution with slower clock rates, resulting in proportionally less resolution. To adequately characterize and test digital devices with toggle rates of 100 MHz or more, a test system must be able to move incrementally and dynamically at data/clock edges with 1 ns resolution or better. A typical application is characterization of a device’s setup and hold times, which requires incremental movement of data relative to a clock.

To perform this test, data (or clock) is moved relative to the clock (or data) in small increments, allowing full AC characterization of the device. Using the digital subsystem’s multiple time set feature, it is possible to assign a different value for sequence or test step, allowing the clock edge to be incremented through the device’s specified setup and hold timing range.

The solution to providing adequate timing resolution without resorting to 1-GHz or greater timing clock rates is to employ a dynamic timing interpolator, which provides the flexibility to position drive/sense test vectors anywhere within a test step with 1-ns or better resolution — not just on the vector clock’s edge boundary. This flexibility allows users to precisely create vector timing without resorting to work-arounds such as over-sampling, a technique that employs the use of multiple vectors in order to achieve even moderate edge placement resolution. In addition, the ability to “dynamically” program a pin’s timing vastly simplifies the creation/execution of timing Shmoo plots, validation/characterization of a device’s AC parametrics, and easier conversion of WGL, STIL, and VCD test vectors. Performing these tests with an instrument that supports only “static” timing per pin requires much longer test times and in some cases, the instrument’s capabilities may not be adequate for the application.

The table highlights the capabilities of the advanced PXI digital I/O digital subsystem with a timing per-pin architecture, compared to a singular timing architecture.

Figure 4. Setup and hold Shmoo plots.
By combining the features of a timing per-pin architecture with software tools, the dynamic performance of digital and mixed signal devices can be readily characterized. For example, by employing a two-dimensional Shmoo plot, a device’s performance can be characterized based upon power supply variations or other parameters. Returning to the setup and hold example, Figure 4 details Shmoo plots for these two parameters versus power supply variations. In each case, test vectors were applied to the DUT over a range of timing and power supply conditions with pass/fail results being displayed for each specific operating condition.


The next generation of PXI digital instrumentation offers the capabilities and test features normally found only in proprietary ATE semiconductor systems. With the advent of these new, advanced digital subsystems, PXI-based semiconductor test solutions can now offer a broader range of test capabilities and features for digital, mixed-signal, and RF test applications. Offering comparable features and performance to proprietary or “big iron” ATE, today’s PXI systems offer compelling test solutions for verification, focused production, and failure analysis applications.

This article was written by Mike Dewey, Director of Marketing at Marvin Test Solutions, Irvine, CA. For more information, Click Here .

NASA Tech Briefs Magazine

This article first appeared in the April, 2016 issue of NASA Tech Briefs Magazine.

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