To perform an input leakage test, the DUT is powered up and the PMU pin is set to Force Voltage/Measure Current Mode. At each input voltage setting, the PMU measures the current being drawn by the input and then verifies the value against the DUT specification. The actual test voltage that the PMU is sourcing can be measured as well. The testing technique can also be used for VIL and VIH testing.
For measuring/characterizing the input protection diodes connected to the device’s ground and VCC pins, the PMU is configured for force voltage/measure current with the voltage stepped in small increments in order to produce V-I curve for each diode. The device begins to conduct at a junction voltage of about 0.7 volts.
AC Parametric Test Capabilities
To adequately address the capabilities and functionality found in proprietary big iron ATE digital instrumentation, today’s PXI-based digital subsystem must have flexible and dynamic timing per-pin or channel capability. Unlike existing 3U PXI digital subsystems that employ a “singular” timing system in which all I/O channels are clocked with the same clock edge, a dynamic timing per-pin system provides the flexibility to position data independently and dynamically on a perchannel basis. Additionally, data formatting (e.g. non return to zero or return to zero, etc.) offers added flexibility when emulating complex bus timing, or if testing for pulse width sensitivity. With these dynamic timing features and data formatting, a PXI-based test system can offer the test capabilities that are comparable to big iron ATE systems.
Dynamic timing implies the ability to move edges anywhere within a test step with adequate resolution. The challenge for a singular timing system is that edge placement will be limited to a rising or falling edge of the vector clock rate, and edge placement will be fixed for a complete vector burst. For example, if the vector clock rate is 100 MHz, edge placement will be limited to 5 ns resolution with slower clock rates, resulting in proportionally less resolution. To adequately characterize and test digital devices with toggle rates of 100 MHz or more, a test system must be able to move incrementally and dynamically at data/clock edges with 1 ns resolution or better. A typical application is characterization of a device’s setup and hold times, which requires incremental movement of data relative to a clock.
To perform this test, data (or clock) is moved relative to the clock (or data) in small increments, allowing full AC characterization of the device. Using the digital subsystem’s multiple time set feature, it is possible to assign a different value for sequence or test step, allowing the clock edge to be incremented through the device’s specified setup and hold timing range.
The solution to providing adequate timing resolution without resorting to 1-GHz or greater timing clock rates is to employ a dynamic timing interpolator, which provides the flexibility to position drive/sense test vectors anywhere within a test step with 1-ns or better resolution — not just on the vector clock’s edge boundary. This flexibility allows users to precisely create vector timing without resorting to work-arounds such as over-sampling, a technique that employs the use of multiple vectors in order to achieve even moderate edge placement resolution. In addition, the ability to “dynamically” program a pin’s timing vastly simplifies the creation/execution of timing Shmoo plots, validation/characterization of a device’s AC parametrics, and easier conversion of WGL, STIL, and VCD test vectors. Performing these tests with an instrument that supports only “static” timing per pin requires much longer test times and in some cases, the instrument’s capabilities may not be adequate for the application.
The table highlights the capabilities of the advanced PXI digital I/O digital subsystem with a timing per-pin architecture, compared to a singular timing architecture.
By combining the features of a timing per-pin architecture with software tools, the dynamic performance of digital and mixed signal devices can be readily characterized. For example, by employing a two-dimensional Shmoo plot, a device’s performance can be characterized based upon power supply variations or other parameters. Returning to the setup and hold example, Figure 4 details Shmoo plots for these two parameters versus power supply variations. In each case, test vectors were applied to the DUT over a range of timing and power supply conditions with pass/fail results being displayed for each specific operating condition.
The next generation of PXI digital instrumentation offers the capabilities and test features normally found only in proprietary ATE semiconductor systems. With the advent of these new, advanced digital subsystems, PXI-based semiconductor test solutions can now offer a broader range of test capabilities and features for digital, mixed-signal, and RF test applications. Offering comparable features and performance to proprietary or “big iron” ATE, today’s PXI systems offer compelling test solutions for verification, focused production, and failure analysis applications.
This article was written by Mike Dewey, Director of Marketing at Marvin Test Solutions, Irvine, CA. For more information, Click Here .