These patents cover such topics as Flash EEPROM and DRAM device, high storage capacity, cell size, cell layout, product material, etching masking material, photolithography technique, narrower spacing between adjacent line patterns, high packing density of pattern line pitch, and smaller chip sizes.
These patents cover such topics as forming Flash EEPROM and non-volatile semiconductor memory, memory cell with non-volatile device DRAM & SRAM cells, self-aligned non-volatile device, forming polysilicon layers, forming dielectric layers, and creating gate control. They also cover guiding gate, creating two isolation regions, self aligned source and drain regions, MOS transistors, semiconductor substrate trench isolation, DRAM cell, SRAM cell.
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