Physicist Joseph Vella, left, and David Graves with figures from their paper. (Photos: Ben Marshall for photo of Vella; Princeton University Department of Chemical and Biological Engineering for photo of Graves. Collage: Kiran Sudarsanan.)

The information age created over nearly 60 years has given the world the internet, smart phones, and lightning-fast computers. Making this possible has been the doubling of the number of transistors that can be packed onto a computer chip roughly every two years, giving rise to billions of atomic-scale transistors that now fit on a fingernail-sized chip. Such “atomic scale” lengths are so tiny that individual atoms can be seen and counted in them.

With this doubling now rapidly approaching a physical limit, the U.S. Department of Energy’s (DOE) Princeton Plasma Physics Laboratory (PPPL) has joined industry efforts to extend the process and develop new ways to produce ever-more capable, efficient, and cost-effective chips. Laboratory scientists have now accurately predicted, through modeling, a key step in atomic-scale chip fabrication in the first PPPL study under a Cooperative Research and Development Agreement (CRADA) with Lam Research Corp., a world-wide supplier of chip-making equipment.

“This would be one little piece in the whole process,” said Professor David Graves, associate laboratory director for low-temperature plasma surface interactions and co-author of a paper that outlines the findings in the Journal of Vacuum Science & Technology B. Insights gained through modeling, he said, “can lead to all sorts of good things, and that’s why this effort at the Lab has got some promise.”

While the shrinkage can’t go on much longer, “it hasn’t completely reached an end,” he said. “Industry has been successful to date in using mainly empirical methods to develop innovative new processes, but a deeper fundamental understanding will speed this process. Fundamental studies take time and require expertise industry does not always have,” he said. “This creates a strong incentive for laboratories to take on the work.”

The PPPL scientists modeled what is called “atomic layer etching” (ALE), an increasingly critical fabrication step that aims to remove single atomic layers from a surface one at a time. This process can be used to etch complex three-dimensional structures with critical dimensions that are thousands of times thinner than a human hair into a film on a silicon wafer.

“The simulations basically agreed with experiments as a first step, and could lead to improved understanding of the use of ALE for atomic-scale etching,” said Joseph Vella, a post-doctoral fellow at PPPL and lead author of the journal paper. Improved understanding will enable PPPL to investigate such things as the extent of surface damage and the degree of roughness developed during ALE, he said, “and this all starts with building our fundamental understanding of atomic layer etching.”

The model simulated the sequential use of chlorine gas and argon plasma ions to control the silicon etch process on an atomic scale. Plasma — ionized gas — is a mixture consisting of free electrons, positively charged ions, and neutral molecules. The plasma used in semiconductor device processing is near room temperature, in contrast to the ultra-hot plasma used in fusion experiments.

“A surprise empirical finding from Lam Research was that the ALE process became particularly effective when the ion energies were quite a bit higher than the ones we started with,” Graves said. “So that will be our next step in the simulations — to see if we can understand what’s happening when the ion energy is much higher and why it’s so good.”

Going forward, “the semiconductor industry as a whole is contemplating a major expansion in the materials and the types of devices to be used, and this expansion will also have to be processed with atomic scale precision,” he said. “The U.S. goal is to lead the world in using science to tackle important industrial problems,” he said, “and our work is part of that.”