CCSDS Telemetry Decoder VHDL Core

Goddard Space Flight Center, Greenbelt, Maryland

A flexible Telemetry Decoder Core (TDC) has been designed to decode Consultative Committee for Space Data Systems (CCSDS) encoded telemetry data. The TDC can be used to eliminate costly ground support equipment by placing the telemetry decoding functions in an inexpensive, commercially available field programmable gate array (FPGA) integrated circuit instead of special-purpose printed circuit boards. The TDC can also be used in the design of telemetry systems by enabling end-toend simulation of these systems’ upfront simulation before any hardware is built. The TDC was developed for the Global Precipitation Measurement (GPM) project and because of its success on that project, it will be used to verify telemetry on the Magnetospheric Multiscale (MMS) project.

This portable, comprehensive CCSDS-Compatible Hardware Decoder was written in VHDL (a hardware description language) and has been developed to verify telemetry data in both simulation and lab environments. Since it is written in VHDL, it can be both simulated easily and ported to lab hardware for verification of telemetry data. The TDC has a wide range of flexibility and can fit into different FPGAs from different vendors.

The TDC has a wide range of flexibility as shown in the figure. A number of options can be enabled or bypassed including: a ½ rate Viterbi decoder, a NRZM Converter, a bit interleaver, a Reed Solomon decoder, pseudo derandomization, and a CRC checker. The Viterbi decoder can be either hard or soft decision and can resync itself based upon a user-configurable bit error rate (BER). The TDC also does frame synchronization and can detect standard pseudorandom patterns PN7, PN15, and PN23. It can accommodate a dual source system by processing two sets of frame data streams.

This work was done by Thomas Winkert and Omar Haddad of Goddard Space Flight Center, and Iraj Sardari of MEI Technologies. GSC-16088-1