Theoretical analysis and some experiments have demonstrated that silicon-on-insulator (SOI) 4-gate transistors of the type known as G4FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation of complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G4FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design.
A G4FET, depicted in simplified form in Figure 1, has the same basic structure as does a prior SOI cross-MOSFET (metal oxide/semiconductor field-effect transistor), though the cross-MOSFET is somewhat wider. The cross-MOSFET consists essentially of an inversion-mode and an accumulation-mode MOSFET that share gate and substrate terminals and are oriented perpendicularly to each other. The prior use of the cross- MOSFET involved sequential operation of the inversion-mode and accumulation- mode MOSFETs. In contrast, the use of the G4FET as an in-plane router involves the simultaneous operation of the inversion-mode MOSFET in one inplane direction and the accumulation-mode MOSFET in the orthogonal inplane direction.
Figure 2 schematically shows the DC configuration of the G4FET relevant to its use as a signal router. The drain (D1) of the inversion-mode p-channel MOSFET is biased to VD1, the drain (D2) of the accumulation- mode n-channel MOSFET is biased to VD2, and the source terminals (S1 and S2) of both transistors are grounded. The two drain currents, ID1 and ID2, are perpendicular to each other and can flow at the same time. ID1 depends on minority charge carriers and flows at the surface in the x direction, while ID2 depends on majority carriers and flows at the mid-depth of the silicon film in the y direction. Surface holes and bulk electrons do not recombine because front-gate-induced depletion region isolates them. The top gate can modulate both drain currents — ID1 through regular MOS action and ID2 through vertical-depletion-width modulation. ID1 and ID2 can also weakly modulate each other — an undesirable effect in that it results in some cross-talk. In operation of the G4FET as a router, S1 and S2 would be disconnected from ground and signals would be applied to D1 and D2 for the purpose of coupling them to S1 and S2, respectively. In experiments on a G4FET that had not been optimized for use as a router, square-wave signals of various frequencies from 1 kHz to1 MHz were applied to D1 and D2 simultaneously and were shown to be coupled to S1 and S2, respectively, as desired. Crosstalk was observed, but was found to be within conventional noise margins. This result supports the expectation that the integrity of digital signals could be preserved when using G4FETs as routers.
This work was done by Amir Fijany, Farrokh Vatan, Mohammad Mojarradi, Nikzad Toomarian, Travis Johnson, Elizabeth Kolawa, Benjamin Blalock, Sorin Cristoloveanu, Suheng Chen, and Kerem Akarvardar of Caltech for NASA’s Jet Propulsion Laboratory. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
Refer to NPO-41827, volume and number of this NASA Tech Briefs issue, and the page number.