Complementary metal oxide/semiconductor (CMOS) image sensors would be capable of operation in a time-delayed-integration (TDI) mode. Heretofore, the only semiconductor electronic image sensors capable of TDI have been charge-coupled devices (CCDs), which have dominated the image-sensor market for nearly all applications.

TDI Would Be Implemented in CMOS Circuitry on the basis of an architecture in which APS pixel rows would be mapped to the rows in the array of integrators.
TDI is an advancement upon so called "push broom" imagers in which a one- dimensional imager array (1 × 512, for example) is used from a moving platform such as an airplane or satellite. The long dimension in such imagers is used to divide the ground scene into pixels in the lateral or so-called cross-track direction. Time sampling is used to divide the ground image in the along-track direction.

TDI imagers use a two-dimensional array (32 × 512, for example). The imager is still operated from a moving platform using the "push broom" scheme, however, as a ground pixel moves across the pixels of the imager in the along-track direction (along the 32 pixels of the column in the example above), the TDI imager multiply samples the same ground pixel and then sums or averages these multiple samples in order to improve the signal-to-noise ratio as compared with a simple, one-dimensional push broom imager.

CCDs are ideally suited for TDI, because they use noiseless summing of charge packets, and because the charge packets are naturally moved across the image plane during readout in a CCD. It is a simple matter to essentially move the charge packet in time with the motion of the associated ground pixel. Unfortunately, CCDs are inherently fairly high-power devices (consuming on the order of watts) and their fabrication processing is not fully compatible with integrated CMOS electronics. CMOS imagers have the ability to operate with much lower power (on the order of tens of milliwatts) and allow the integration of control electronics and signal processing on-chip, in order to enable the development of highly compact complete imaging systems, including even analog-to-digital conversion on-chip.

The development of low-noise switched capacitor circuitry, as well as the development of the CMOS active pixel sensor (APS) visible imager, have made it possible in principle to realize TDI in the proposed CMOS image sensors. As shown in the figure, a device according to the proposal would include a CMOS 32 × 512 APS array connected column-wise to a 32 × 512 array of low-noise, high-speed analog charge integrators. These are followed by a one-dimensional array of column-parallel cyclic architecture analog-to-digital converters that service the column-parallel array of integrators.

As a ground pixel moves its focus from pixel to pixel along the column of the APS array, the signal from this ground pixel is multiply sampled, and each sample is integrated onto the storage capacitor on one integrator in the integrator array. Since the ground pixel moves from pixel to pixel in the imaging array, the TDI imager must continually keep track of which pixel's output is added to which integrator. After a given ground pixel has moved through all 32 rows, the output of the corresponding integrator is sent to the ADC for digitization, and the integrator is reset so that it can begin the integration of the new ground pixel that moves into the field of view. Of course, all 32 pixels in the column must be connected in turn to the appropriate integrators in the time it takes for a ground pixel to move from one imager pixel to the next. The signal is dumped in a snapshot mode that eliminates motion artifacts that would otherwise be caused by the fact that each imager pixel is addressed at a slightly different time.

Within the general layout and mode of operation described above, the proposal encompasses several alternative operating schemes and readout-circuit designs. Each represents a different trial solution to achieve optimum performance with regard to sensitivity, low power consumption, high-speed digital readout, and minimization of the non-imaging-area of the chip. These schemes and designs are too complex to describe within the space available for this article; interested readers should request more information, as noted below.

This work was done by Bedabrata Pain, Thomas Cunningham, Guang Yang, Monico Ortiz, and Brita Olson of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp  under the Electronics & Computers category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

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Refer to NPO-20802, volume and number of this NASA Tech Briefs issue, and the page number.


This Brief includes a Technical Support Package (TSP).
CMOS Image Sensors Capable of Time-Delayed Integration

(reference NPO-20802) is currently available for download from the TSP library.

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