“Flip chip on board (FCOB) with high thermal conductivity and tailored coefficient of thermal expansion (CTE)” denotes a developmental concept for relatively inexpensive, lightweight packaging of electronic circuits to accommodate high densities of components and of interconnections. The concept addresses several issues that pertain to flip-chip performance and reliability and to the integration of flip chips with other components: These issues include minimization of undesired mismatches of CTEs between flip chips and printed-wiring boards (PWBs), removal of heat from high-power flip chips, and the need to maximize stiffness while minimizing weight.

These Temperature Maps were computed in a finite-element simulation of thermal conditions on a PWB on which four heat-generating flip chips are mounted. For each of the two cases shown here,the peak temperature mentioned in the text was calculated as an average over all nodal values within the “footprints” of the flip chips.

Usually, a conventional PWB is made of an epoxy-matrix/glass-fiber laminate, called “FR-4,” with copper surface layers that can be etched to form signal and power conductors. A PWB of the present developmental type includes a core layer that contains a carbon cloth, sandwiched between FR-4 outer layers. Typically, the thickness of the carbon- cloth layer is about one-third the overall thickness of the laminate.

Carbon cloth is used in the core layer because it has several properties that are desirable with respect to the issues mentioned above. These properties include the high thermal conductivity of carbon fibers (up to 1,100 W/m⋅K), low CTE [<<10–6 (°C)–1 in some cases], low mass density [≈0.07 lb/in.3 (1.9 kg/m3) for carbon versus ≈0.1 lb/in.3 (2.8 kg/m3) for aluminum], and high stiffness [up to ≈42 Mpsi (≈290 GPa) for carbon versus ≈10 Mpsi (≈69 GPa) for aluminum].

The use of a carbon-fiber core layer to increase the thermal conductance of a PWB and thus the ability of the PWB to dissipate heat offers two benefits. One benefit is higher reliability: It has been estimated that in many cases, lowering the temperature of operation of electronic components by 10 °C approximately doubles the mean time between failures of the components. The other benefit is that lower operating temperatures enable components (especially data processors) to function at greater speeds and efficiencies.

Thus far, thermal testing of specimens and finite-element modeling of carbonfiber-core FCOBs have shown the potential for matching of CTEs and lowering operating temperatures of components.

In one example in the temperature analysis (see figure), the peak temperature under a flip chip was estimated to be ≈277 °F (≈136 °C) on a conventional FR-4 PWB but only ≈129 °F (≈54 °C) on a carbonfiber-core PWB.

In one example in the CTE-mismatch analysis, the effective CTE of the region of a carbon-fiber-core where flip chips would be mounted was found to be ≈ 1.0 × 10–5 (°C)–1; in contrast, the corresponding CTE of a conventional FR-4 PWB was found to be ≈2.1 × 10–5 (°C)–1. Thus, the carbon-fiber core exhibits less CTE mismatch with the chip substrate material — silicon — for which the CTE ranges from 3 × 10–6 to 5 × 10–6 (°C)–1. Ultrasonic imaging of carbon-fiber-core FCOB specimens after thermal tests of the specimens revealed that the thermal tests did not result in any detectable increase in the incidence of failures of flip-chip-mounting solder joints.

This work was done by Eyan Lee and William E. Davis of Applied Material Technologies, Inc., for Glenn Research Center.

Inquiries concerning rights for the commercial use of this invention should be addressed to

NASA Glenn Research Center
Commercial Technology Office
Attn: Steve Fedor
Mail Stop 4–8
21000 Brookpark Road
Ohio 44135.

Refer to LEW-16890.