A hardware-command-decoding application-specific integrated circuit (HCD ASIC) is designed to decode digital command signals transmitted from a ground station to a spacecraft (uplink commands). Implemented in the ASIC is a portion of the spacecraft uplinkprotocol specified in the widely used Consultative Committee for Space Data Systems (CCSDS) international standard. A terrestrial version might be useful, for example, in decoding digital command signals for a mobile robot. The HCD ASIC performs functions that previously required several different circuits, while taking up less room and consuming less power. Implemented on a single silicon-based chip in a 256-pin package, this ASIC resists both permanent damage and single-event upsets (bit-flips) produced by ionizing radiation. Tested ASICs are available to users.

This ASIC is designed to operate in conjunction with (1) an engineering flight computer (EFC) connected via an intersubassembly bus (ISB), (2) critical relay controllers (CRCs), and (3) a start-up programmable read-only memory (PROM). The figure shows the hardware and software functional blocks of the HCD ASIC. In addition to the HCD block, this ASIC contains a block that performs error detection and correction (EDAC) on data that comes from the PROM, a CRC block, an ISB interface block, and a fault-detection unit (FDU). The blocks are integrated in a highly efficient manner to make them fit together on the single chip. A key feature of this ASIC is the ability to accelerate processing in the detection of "start" data sequences and in EDAC, using parallel processing. Another key feature of this chip is the use of the double-buffer method for read/write/status and for resolving overruns of data.

The HCD ASIC performs functions that previously required several different circuits, while taking up less room and consuming less power.

The data from the PROM are in the form of 16-bit words with 6 parity bits. The PROMEDAC corrects any single-bit error and signals to the ISB bus master that it has done so. When the PROMEDAC finds an uncorrectable error, it gives notice to that effect by sending out a "bad" parity signal on the data-bus portion of the ISB.

The FDU includes a watchdog timer and provides interrupt-control support, reset control, and eight discrete outputs that facilitate the exchange of information on the integrity and operational condition of the system.

The ASIC receives a serial, digital data stream as well as a clock signal and a "lock" signal from the uplink data receiver. Two parallel-processing algorithms are used in the HCD block, where traditionally a serial process has been used. "Start" detection is performed by checking the 32 most recent bits of data with the acquisition sequence followed by the "start" sequence. EDAC is also performed by using Perlman's (1980) serial algorithm in a parallel process. A search of uplink data is performed, depending on the "active" or "inactive" state of the HCD. Whenever the "lock" signal is not present, the ASIC goes into the "inactive" state and ignores the uplink. When the "lock" signal appears, the ASIC goes into the "search" state and starts searching uplink data for the "start" sequence. It then goes into the "decode" state and starts decoding code blocks.

EDAC is performed on each code block, and the code block is placed in a data buffer accessible via software. A "tail" sequence forces the ASIC back into the "search" state. Software must fetch a code block from the data buffers (described below) and perform the format checks and interpretation of data. The ASIC presents code blocks to software that pieces them together to form larger frames.

The ASIC contains two data buffers that are used to pass each uplink code block to the software. Each buffer consists of four 16-bit registers and can hold one 64-bit code block. These two data buffers enable the software to read one buffer while the hardware loads the other buffer.

The CRC block communicates directly with the HCD block. It contains data on the state of the command-and-data subsystem of the spacecraft and on the configurations of other parts of the spacecraft. The CRC block includes CRC and EFC mask registers, into which data are written from the ground by use of a specific transfer-frame format. The CRC block includes an EFC/CRC interface that comprises three registers that store 24 volatile CRC bits. These bits are readable and writable through the ISB. An HCD/CRC interface also provides 24 nonvolatile control of relays. Relay state may be changed ahead through the ISB.

The ISB interface connects the ASIC to the outside world through the ISB bus. It also serves as the main interface between the EFC and the command-and-data subsystem. It generates all necessary ISB bus timing signals.

This work was done by Gary S. Bolotin, James A. Donaldson, Huy H. Luong, and Steven H. Wood of Caltech for NASA's Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

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