An application-specific integrated circuit (ASIC) has been developed as a prototype of neuroprocessors for real-time diagnosis and control of automotive engines. The application of this ASIC was previously reported in "Neuroprocessor for Detecting Misfire in an Automotive Engine" (NPO-20044) NASA Tech Briefs, Vol. 21, No. 12 (December 1997), page 60. The neuroprocessor is configured as a recurrent neural network, which differs from a conventional feedforward neural network in that the inputs to some of the neurons can include feedback signals in the form of time-lagged, weighted outputs from other neurons. Thus, the neuroprocessor responds not only to current inputs but also to the recent history of inputs.
As was previously reported, the neuroprocessor ASIC is implemented in high-speed complementary metal oxide/semiconductor (CMOS) very-large-scale integrated (VLSI) circuitry with a bit-serial architecture. By employing bit-serial techniques, this architecture makes for compactness and cost-effectiveness because (1) it entails fewer interconnections and less hardware than does bit-parallel architecture and (2) efficiency is
increased through the periodic, repetitive use of the same circuitry in a time multiplexing scheme to implement successive layers in the neural network. Because the same neurons are reused in successive layers of the neural network, the total number of neurons need not exceed that of the largest layer. This architecture also affords flexibility to realize different neural-network configurations for different diagnostic or control functions; that is, multiple tasks can be performed in rapid succession, using the single neuroprocessor ASIC, by loading the synaptic-connection weights for each task at the time of that task.
The ASIC includes a module containing 16 neurons, a global controller, a read-only memory (ROM) containing a lookup table that specifies a bipolar sigmoid activation function of a neuron, a random-access memory (RAM) that serves as a register of neuron states, and a RAM containing synaptic weights (see figure). In this physical VLSI realization, each neuron receives, as inputs, synaptic weights and activation-function values from input nodes or neurons of a preceding layer in bit-serial fashion; each neuron responds by performing multiplication-and-accumulation operations that yield the value of the activation function for the given inputs.
The global controller generates the control logic and orchestrates the movement of data, as needed, to enable the rest of the ASIC to perform the required task. When a "run" command is issued, the global controller provides control signals to the 16 neurons, the RAMs, and the ROM to proceed with the desired neurocomputation. Input activations and synaptic weights are read out of the neuron-state and synaptic-weight RAMs, respectively, and sent to the neurons. Upon completion of a forward pass through the module of neurons, the global controller returns to an idle state, awaiting receipt of the next "run" command.
This work was done by Raoul Tawel of NASA's Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to
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