The figure shows a complementary metal oxide/semiconductor (CMOS) integrated circuit that contains all of the electronic circuitry of a programmable active-pixel-sensor digital camera. Heretofore, digital cameras have been assembled from charge-coupled-device (CCD) chips, separate analog-to-digital converters, and separate units that perform timing, control, and interface functions; each unit adds to the size, cost, and power consumption of a camera. The present single-chip camera is a prototype developed for many applications within the space program. It also meets the demands of a large potential market for compact, low-power-consumption, and (eventually) inexpensive portable digital cameras. The chip has been packaged as a low-power camera occupying only 1 cm3 (0.06 in.3), exclusive of optics, with an all-digital 5-wire serial interface. The chip is also being incorporated, along with a wireless interface unit, into a battery-operated camera with a volume of less than 32 cm3 (2 in.3).
Included on the chip are analog-to-digital converters (ADCs) and full timing, control, and interface circuitry. All analog reference voltages for imaging and digitization are generated by programmable digital-to-analog converters (DACs) that are also included on the chip. Thus, the camera contains a complete digital interface. Through a single digital input pin, the chip can be programmed to perform a variety of imaging operations and/or to establish the required interface configuration; this capability facilitates integration with a variety of external digital systems.
The image-sensor portion of the chip is a 256 × 256 array of photogate active pixel detector circuits, with a 20.4-µm pixel pitch and a 21-percent fill factor. Each pixel includes a source follower for coupling the pixel output to a column bus. Next to the sensor array is the array of ADCs, of which there are 256 in a column-parallel arrangement. Each ADC uses a successive approximation algorithm with internal correlated double-sampling and offset-correction circuits to reduce noise, designed to yield an output with 10 bits of resolution. To decrease power consumption while an image is not being acquired, the chip has a low-power (40-µW) idle mode, in which the DACs, pixel source followers, and ADCs are disabled.
The chip can be programmed in order to set the desired exposure time and to operate in any of a number of imaging modes. The amount of data and power required for an image may be reduced by programming the chip to use a smaller window contained within the 256 × 256 array and by subsampling the pixels within the desired window. Although designed primarily to take still pictures, the chip can also be programmed to acquire images continuously. After acquiring a digital still image, the chip automatically enters the low-power idle mode.
The chip can be programmed to produce serial or parallel data output in a variety of formats. It can be made to implement full- or half-duplex protocols and to generate vertical and horizontal frame-synchronizing signals. It can accommodate a variety of input and output data rates and internal clock rates; it can even operate with separate input command and output data rates or receive asynchronous input command data at particular bit rates with no input clock. This flexibility is achieved by use of separate programmable clocks, derived internally from the input clock, to control various operations on the chip. The chip can support frame rates up to 14 Hz with serial output or 60 Hz with parallel output. During full operation with serial output, the total power consumed by the chip is about 20 mW.
This work was done by Timothy Shaw, Bedabrata Pain, Brita Olson, Robert Nixon, Eric Fossum, Roger Panicacci, and Barmak Mansoorian of Caltech for NASA's Jet Propulsion Laboratory. For further information contact Bedabrata Pain at (818) 354-8765. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to
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