There is a need for rad-hard crystal stabilized clock sources with at least 300 krad of total ionizing dose (TID) immunity. A common solution has been to spot-shield a commercial off-the-shelf part or enclose it in a vault. Rad-hard clock sources are needed for main electronics boards (MEBs) and readout electronics that need to operate in hazardous space environments. Remote sensing and telemetry require that the readout circuits be co-located with the sensors, which can be separated by an arbitrary distance from the data processing electronics.
A locally generated clock signal allows the readout to generate its own clock signals and to transmit the resulting data to a remote receiver. If a crystal stabilized carrier signal was available, the readout could derive a clock signal that is an integral submultiple of that carrier and use the data generated from the clock signal to modulate the carrier. The radiation hardened by design (RHBD) CMOS crystal oscillator may be used directly or scaled in frequency to clock an application circuit.
The RHBD CMOS crystal oscillator is a comparator-based Pierce oscillator that uses a piezoelectric crystal for accurate and stable frequency generation. The oscillator scheme differs from classic Pierce oscillators that rely on at least one inverter to achieve the required gain. In the RHBD CMOS crystal oscillator, a high-speed comparator provides the gain with the crystal and linearizing feedback resistor connected between the comparator output and the inverting input. The non-inverting input of the comparator can be driven from a DC signal source, such as a resistor divider, voltage reference, or digital to analog converter (DAC), for a variable common mode in the feedback signal or a variable duty cycle clock signal. Having the ability to adjust the duty cycle of the oscillator signal allows the system to compensate for radiation-induced changes such as input offset.
The comparator is a monolithic CMOS rail-rail design with a proportional to absolute temperature (PTAT) bias cell fabricated with enclosed layout transistor (ELT) devices and dual guard rings. The ELTs provide high immunity to TID-induced leakage and the dual guard rings provide immunity to single event latch-up (SEL). Together, the ELTs, dual guard rings, and duty cycle adjustment ensure robust operation of the circuit even in the presence of high TID and heavy ions.