A method of correcting for defective pixels in an integrated-circuit image sensor of the active-pixel sensor (APS) type has been proposed. The corrections would be made by additional readout circuitry on the image-sensor chips. By making it unnecessary to discard sensor chips that contain limited numbers of scattered defects, the method would increase effective production yields and thereby lower the costs of individual image sensors.

Registers Functioning as Content-Addressable Memories would store the row and column coordinates of defective pixels. As many as four addresses, each 10 bits wide, could be stored for identifying defective individual pixels or defective entire rows or columns of pixels.
Two issues arise in trying to correct for defective pixels: how to store information on the locations of these pixels and how to process pixel outputs in the readout process. Because most of the area of an image-sensor chip is occupied by the array of pixels, there is little room for circuitry for storing addresses of defective pixels. Accordingly, the coordinates of any defective pixels and of any defective entire rows or columns of pixels would be stored in several registers (see figure), the number of registers being based on a practical upper bound on the number of pixels, rows, or columns likely to be defective. In the initial proposed design, there would be four such registers, and they would be embedded in the on-chip timing and control circuitry.

The set of registers would function in the manner of a content-addressable memory. During readout, the current row and/or column address would be applied to this memory and a flag would be generated if the current address matched the stored address, signifying that the current pixel, row, or column is defective.

The method admits of alternative designs corresponding to alternative ways to respond to a "defect" flag. The simplest approach is to design the readout control logic circuit to simply skip an entire row that contains even one bad pixel, skip an entire bad column, and increment to the next row or column. In this approach, it would suffice to store only the row address of a single bad pixel.

Another approach would involve substituting, for each defective pixel, the average of readouts from the eight surrounding pixels. This approach would be less practical or attractive for on-chip implementation because it would necessitate more circuitry occupying more chip area. The additional circuitry would be necessary for storing information from three rows at a time (the previous row, the current row, and the next row to be read out) plus processing of information from three rows and columns at a time.

A more practical approach would involve replacing the output from a dead pixel with a copy of the output from a neighboring pixel that was read out previously. The copy could be obtained by use of a simple single-pixel delay line.

An essential step in this method would be a procedure for testing to locate defective pixels, rows, and columns and for writing the addresses of these pixels, rows, and columns in the registers. In the first generation of image sensors designed according to this method, the testing and the programming of registers would probably be performed manually. Eventually, it should be possible to add automatic testing and programming circuitry to the chips.

This work was done by Nick Doudoumopoulos, Roger Panicacci, and Eric H. Fossum of Photobit for Johnson Space Center. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp  under the Electronic Components and Systems category. MSC-22827