The new high-speed interconnect standards will dramatically change the way computer and communication systems are designed. Switch- based systems will be the winners in new high-performance designs, and RapidIO is positioned to be one of the more popular serial switch-based standards.

Figure 1: The Motorola 857T Processor Daughter Card.
Figure 2: The Xilinx Virtex-II FPGA Development Board.
Figure 3: A RapidIO System Block Diagram.
Internet bandwidth requirements are being driven by consumers. Ever-increasing demand for continuous and increasingly multi-media-rich Internet access requires rapid, efficient processing and transmission of data. The computing and networking industry has responded by increasing microprocessor clock speeds and creating a new class of network- optimized processors that support this data processing need. Increasingly, getting the data on and off the chip — not the internal processing rate — is the limit to system performance.

The RapidIO architecture is an electronic data communications standard for interconnecting microprocessors, digital signal processors, communications and network processors, system memory, and peripheral devices on a circuit board using a backplane. It is a packet-switched, point-to-point technology used for passing data and control information within embedded systems — primarily in networking and communications equipment. Designed for networking and communications equipment, enterprise storage, and other high-performance embedded markets, the RapidIO architecture addresses the demand for higher performance by offering bandwidth, software independence, fault tolerance, and low latency.

The RapidIO standard is conceptually similar to the Internet Protocol (IP) specification and defines a physical layer capable of supporting throughputs exceeding 10 Gbps utilizing low-voltage differential signaling (LVDS) technology. It is transparent to application software, and does not require special device drivers. Additionally, it has no impact on the operating system software. A rich variety of features are provided in the RapidIO interconnect including high data bandwidth capability, support for high-performance I/O devices, and providing globally shared memory, message passing, and software managed programming models.

Designers wishing to quickly develop RapidIO-based systems require a flexible hardware development platform, one on which they can try out a variety of system architecture alternatives, develop and optimize applications code, and integrate various IP. A flexible development platform has been created for RapidIO based on a Motorola 857T processor daughter card and a Xilinx Virtex-II FPGA development board. These cards, when combined, create a flexible hardware environment on which the Xilinx RapidIO physical layer LogicCore™ has been integrated to create a complete RapidIO system.

The Motorola 857T Processor daughter card (see Figure 1) contains a set of standard peripherals and memory, and runs Linux. It connects to the Virtex-II development board via a connector and can access all the resources on the FPGA, the memory, and interfaces. The embedded Linux operating system running on the daughter card makes it easy to create code to exercise the RapidIO core. When connected with a cable to a duplicate set of boards, RapidIO traffic may be sent between the systems, and allows performance and system architecture evaluation and trade-offs.

The Virtex-II Development board (see Figure 2) contains a Xilinx Virtex-II FPGA, SDRAM, Flash memory, a PCIBus interface connector, and several modular connectors for interfacing to a variety of daughter cards. This interface is part of the Avalon Reference Design SystemT™ and allows a variety of hardware, IP cores, and software to be used to create a complete development environment.

The system block diagram in Figure 3 shows the hardware features of the RapidIO development kit. The daughter card provides the processing power for the reference design and communicates over the connector to the user interface portion of the RapidIO IP Core in the FPGA on the development board. The data to and from the RapidIO IP Core is transferred to another RapidIO system via the Serializer Deserialized block in the FPGA. Eight bits of data are transferred at a time over the LVDS signal pairs.

The Motorola 857T runs an embedded version of the Linux operating system and serves up Web pages at the request of the other processor daughter card in the system. The Web page transactions are sent over the RapidIO data communications link based on the transaction requests of the host and server processor.

The LogiCORE RapidIO Physical Layer Interface, a fixed netlist solution for the RapidIO interconnect, is a preimplemented and fully tested module for Xilinx Virtex®-II series FPGAs. The pinout for the device and the relative placement of the internal logic are predefined. Critical paths are controlled by a constraints file, which ensures predictable timing, significantly reducing engineering time required to implement the RapidIO Physical Layer portion of a design. Resources can be focused on unique user application logic in the FPGA and on the system-level design. The FPGA devices meet all required electrical and timing parameters including AC output drive characteristics, setup, hold, and clock-to-output as stated in the 250-MHz RapidIO AC specification.

This article was written by Dave Connolly and Warren Miller of Avnet Design Services, and Rakesh Ghai of Motorola Semiconductor. For further information, contact Avnet Design Services at 800-408-8353 or visit