The Dynamically Configurable Pipeline is a concept for the rapid implementation of pipelined computational algorithms in configurable hardware such as field programmable gate arrays (FPGAs). The approach, especially in its phase-coherent incarnation, allows a high level of sharing of floating-point resources among multiple computations. The concept features a simple tag-based control scheme and a sparse-pipeline allocation approach that enables all the stages of an arithmetic pipeline to be processing simultaneously, with multiple computations allocated to the same pipeline. Thus, the approach increases hardware resource utilization and reduces power consumption.

This method provides a simpler interface for algorithm designers as compared to the current state-of-the-art of development environments. The method provides a design that can be easily modified to change the algorithm, unlike the traditional direct implementation in a systolic array (direct datapath). The approach is significantly simpler than the alternative of a custom soft processor, which can also provide an interface more accessible to non-hardware designers, but requires substantial initial development not related to the desired computation.

This work is differentiated from prior art by its application of a configurable datapath between pipelined functional units, its use of tag-based configuration control, and a hardware reuse method based on simple relationships between the functional unit latencies and the data arrival interval. The configurable datapath allows functional units to not be dedicated to a particular computation, but to be reused for an arbitrary number of computations. The tag-based control eliminates the complexity of centralized pipeline control. The reuse scheme addresses the complicated problem of managing limited configurable resources without a complicated problem formulation and framework to accomplish scheduling and allocation on the hardware resources.

The method has wide applicability to pipelined numeric computations and configurable hardware, which spans the entire field of numeric computation. More specifically, the method could be incorporated into any synthesis system for pipelined computations. Configurable chip manufacturers could incorporate the design approach. Hybrid general-purpose, configurable computing systems could use the approach in their synthesis systems.

This work was done by Robert Shuler and David Rutishauser of Johnson Space Center. MSC-25161-1

NASA Tech Briefs Magazine

This article first appeared in the February, 2015 issue of NASA Tech Briefs Magazine.

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