Semiconductor electronic devices and circuits based on silicon carbide (SiC) are being developed for use in high-temperature, high-power, and/or high-radiation conditions under which devices made from conventional semiconductors cannot adequately perform. The ability of SiC-based devices to function under such extreme conditions is expected to enable significant improvements in a variety of applications and systems. These include greatly improved high-voltage switching for saving energy in public electric power distribution and electric motor drives; more powerful microwave electronic circuits for radar and communications; and sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines.

Silicon carbide occurs in many different crystal structures, called polytypes. Despite the fact that all SiC polytypes chemically consist of carbon atoms covalently bonded with equal numbers of silicon atoms, each SiC polytype has its own distinct set of electrical semi- conductor properties. While there are more than 100 known polytypes of SiC, only two of them are commonly grown and commercially available in a form acceptable for use as an electronic semiconductor. Both of these polytypes, denoted 4H-SiC and 6H-SiC, respectively, have hexagonal crystal structure. Another polytype, denoted 3C-SiC, has cubic crystal structure and, with respect to use in electronic devices, offers significant benefits over conventional hexagonal SiC polytypes. However, all previous attempts to reproducibly grow 3C-SiC layers have yielded inferior crystals with high densities of defects that make the crystals unusable for realizing their beneficial electronic properties.

Figure 1. These Schematic Cross Sections of a mesa on a hexagonal-SiC wafer depict the process of growing 3C-SiC by step-free surface heteroepitaxy.

Recently, a growth process denotedstep-free surface heteroepitaxy has been shown to produce greatly improved 3C-SiC single- crystal films that should enable the reproducible realization of the beneficial properties of 3C-SiC for electronic devices. In this process, the 3C-SiC films are produced on arrays of mesa surfaces that are patterned into commercially available hexagonal-SiC wafers. Figure 1 depicts the subprocesses that affect a mesa. First, reactive-ion etching is performed to form a pattern of trenches into the surface of the wafer, thereby forming the mesas as the unetched surface areas between trenches. The cross section at the top of Figure 1 shows tightly bonded Si-C bilayers along the crystallographic basal plane, along with single bilayer height steps on the mesa surface that arise because of an unavoidable tilt angle (typically about 0.1°) that is attributable to polishing of the crystal surface at the wafer factory.

Next, pure step-flow homoepitaxy, wherein new reactants become incorporated into the crystal only at the surface steps (which are sites favorable to bonding), is used to grow 4H-SiC from the surface steps on top of each mesa over to the edge of the mesa. Upon completion of this subprocess, the top surface of the mesa is free of atomic steps. That fact that all growth takes place at the steps enables replication of the hexagonal crystal structure of the substrate in this initial epilayer.

After the step-free basal-plane mesa surface of the hexagonal SiC crystal has been established, heteroepitaxial growth of a film having the cubic SiC crystal structure is then initiated by lowering the growth temperature. The lower growth temperature enables the growth of 3C-SiC on the basal plane via nucleation of 3C-SiC islands, followed by lateral step-flow expansion. Well-behaved thermodynamic control of polytype occurs in the absence of surface steps, so that the film grows in the cubic crystal structure rather than a hexagonal crystal structure. In experiments, the step-free interface between the hexagonal and cubic polytypes was found to eliminate the double- positioning boundary defects commonly found in previous 3C-SiC heterofilms. However, it was also discovered that the initial 3C-SiC bilayers must be nucleated slowly to obtain 3C-SiC films free of stacking-fault defects.

Figure 2. 3C-SiC Films were grown on flattened mesas, then thermally oxidized to reveal crystal defects. The defect-free film shown on the right was made by use of step-free surface heteroepitaxy.

Figure 2 shows two 0.2-by-0.2-mm mesas topped with 3C-SiC films nearly 2 μm thick and thermally oxidized to reveal stacking-fault defects. As indicated in the figure, the mesas were grown with different initial island-nucleation rates. It has been suggested that what is needed during the initial stages of growth to obtain a defect-free 3C-SiC film is the single-island growth mode, in which a single 3C island nucleates and expands laterally to cover the mesa before a second interfering 3C island nucleates. It has been further suggested that the multiple-island growth mode, depicted at the bottom of the figure, is acceptable after the initial bilayers of the 3C-SiC film have been grown in the single-island mode. In experiments, it was found that 4H-SiC/3C-SiC atomic lattice spacing mismatch was at least partially relieved, without generating stacking faults that threaded to the surface of the film.

The step-free surface heteroepitaxy process is believed to be applicable to growth of heterofilms of materials other than 3C-SiC. Further growth and characterization experiments are in progress, including experiments on the fabrication of prototype 3C-SiC devices and attempting step-free surface heteroepitaxy of GaN films on 4H- or 6H-SiC substrates.

This work was done by Philip G. Neudeck and J. Anthony Powell of Glenn Research Center.

Inquiries concerning rights for the commercial use of this invention should be addressed to:

NASA Glenn Research Center
Commercial Technology Office
Attn: Steve Fedor
Mail Stop 4–8
21000 Brookpark Road
Cleveland, Ohio 44135

Refer to LEW-17186.