A key measure driving performance in semiconductor integrated circuits (ICs) is reliability. As ICs continue to become smaller and chip complexity increases, manufacturers need to ensure they can continue to provide the same level of reliability to their customers for mission-critical end applications.
While wafer level reliability tests have long been used to provide insights into variability in processes and degradation, these increased demands from new technology trends and chip complexity drive engineers to look for methods to increase reliability test data while decreasing cost. Current approaches make tradeoffs between channel count and flexibility but a parallel per pin approach is necessary to address both.
Wafer Level Reliability (WLR) Test Overview
Along the lifetime of an IC, there are two clear times when an increased failure rate is expected: in the beginning with defects during the manufacturing process and at the end as the IC begins to wear out. Optimizations to the production process increase yield but do not help understand what causes products to wear out earlier than expected. Reliability testing gives insight into what processes or mechanisms could cause premature IC failure and estimates the lifetime of an IC.
The typical method used in reliability testing involves operating the device at its usable limits (often around temperature and voltage) to force it to wear out and model its lifetime against known failure mechanisms. These tests are done on built-in structures in the wafer to gather data and ensure it can be done earlier in the manufacturing process.
The failure mechanics usually tested comply with Joint Electron Device Engineering Council (JEDEC) standards for common WLR stresses. They include time-dependent dielectric breakdown (TDDB),hot carrier induced degradation (HCI), and bias temperature instabilities (BTI/NTBI). The wiring setup to test these mechanics on transistors in a wafer includes four source measure units (SMUs), each tied to the Source, Drain, Gate, and bulk terminals and a switching matrix. (Figure 1)
Stress measurement algorithms run on the test data generated from I-V and C-V sweeps. These sweeps are set up as steps in a larger test sequencer that controls the switching from one device under test (DUT) to the next, data acquisition and management, and report generation.
Historically, there have been two approaches to WLR testing: rack and stack, and turnkey. These often employ high-precision box SMUs alongside a high-channel-count switching matrix to sequentially step through the devices being tested. In the rack and stack example, engineers face a high cost per channel, a greater footprint for their test, and an increased test time from the switch matrix.
For example, consider having to perform a stress test on a wafer containing 20 diodes. To perform an I-V sweep on each diode, the SMU would source a voltage, wait the necessary Source Delay time, then measure back voltage and current. If the diode needs two power line cycles (PLCs) 40 ms to settle before a measurement is taken and 10 ms is required to ensure a minimal impact between switching diode connections, then each test in sequence would take at least 50 ms. This means it would take one second to complete all IV tests on one wafer. As the number of wafers and diodes increases, test times can exponentially increase, which is not scalable for today’s fabs.
The turnkey solution optimizes for test time and improves on footprint and channel count at the cost of flexibility. Test teams could encounter difficulty as test requirements change to continue meeting increased demands. Both cases do not scale as the need for more data and lower costs continue to rise.
Modular Software-Connected Approach
With growing demands on production driving the need for smaller, more complex semiconductor chips, test engineers do not have the luxury of leaning on traditional approaches to testing ICs. They need to keep pace while maintaining chip performance and reliability. A clear approach is through adopting a parallel high-channel-density modular solution. A single point of both test equipment cost and time is the switching matrix connecting SMUs to probe points. Wafer test solutions using low-channel-count SMUs incur a high cost per channel that grows as the application scales. Using a switch matrix to mitigate this is common but due to strict requirements on accuracy and precision, these modules can drive just as high of a price tag.
In addition, as outlined in the previous example, incorporating a large switch matrix into a system to connect a small number of SMUs to a substantial number of probe points drives up test time. The NI WLR solution has already begun to improve on these points. Using PXI and high-precision, high-accuracy SMUs, test engineers are able to shorten WLR test cycles from months to days, reduce footprint and minimize power consumption, and enjoy increased flexibility through upgradable channel count and SMU per-pin architecture.
High Speed, High Precision, High Accuracy
A common measure used to model transistors’ performance on a wafer is the Capacitance-Voltage (C-V) test. Test measurements can be used to derive parameters such as oxide thickness, doping concentration, and carrier lifetime. The method used for C-V tests requires setting a bias voltage and performing an AC sweep of current. The PXIe-4135 (Figure 2) is an SMU optimized for high-speed sampling and low current measurements.
Engineers can source the proper bias voltage, generate low-frequency waveforms, read back AC signals, and generate picofarad capacitance measurements all from the same device. This SMU can also generate pulses and read back DUT responses using its 1.8 MS/s digitizer. This allows it to capture both high-speed transient responses and use averaging algorithms to produce highly precise measurements during I-V sweeps.
Smaller, Faster Parallel Test
The benefits of using modular configurable hardware grow as the application grows. The WLR solution can be configured to hold up to 17 system SMU channels or expand to higher-density SMU modules (Figure 3).
Engineers can forgo a switching matrix and set up parallel tests that drastically reduce test time. Instead of having to switch to each new DUT, several can be wired to their own SMU. Configurations can span up to 100 fA-class SMU channels in a single 40U rack (Figure 4).
The WLR solution comes with configuration software — a combination of development software and test management software — to accelerate time to first measurement. Engineers can perform stress tests in two- and four-terminal configurations with things like synchronization, data management, and sequencing pre-built into the application. If test requirements change, test teams can use drivers and APIs built in many languages to quickly modify their applications and update their test management environment.
Wafer reliability test gives manufacturers the ability to make data-driven decisions around process improvements throughout the development cycle. This accelerates the production of reliable, high-performance ICs. Manufacturers are quickly approaching a challenge of scale; traditional approaches will continue to get longer and more expensive, so test teams will need to adopt solutions that help mitigate that. Highly parallel, modular, software-connected solutions dramatically reduce test time at lower costs. They put test teams ahead of the curve and allow them to scale and improve as the semiconductor market continues to evolve and grow.
This article was written by Travis Escoffery, Product Marketing Manager at NI (Austin, TX). For more information, visit here .