Analog-to-digital converters (ADCs) are used in scientific and communications instruments on all spacecraft. As data rates get higher, and as the transition is made from parallel ADC designs to high-speed, serial, low-voltage differential signaling (LVDS) designs, the need will arise to interface these in field-programmable gate arrays (FPGAs). As Xilinx has released the radiation-hardened version of the Virtex-5, this will likely be used in future missions.

High-speed serial ADCs send data at very high rates. A de-serializer instantiated in the fabric of the FPGA could not keep up with these high data rates. The Virtex-5 contains primitives designed specifically for high-speed, source-synchronous de-serialization, but as supported by Xilinx, can only support bit-widths of 10. Supporting bit-widths of 12 or more requires the use of the primitives in an undocumented configuration, a non-trivial task.

De-serializing the bits from high-speed ADCs running at speeds of 50 Msps or more becomes a non-trivial problem in the Xilinx Virtex-5. The bit clock speeds are very high (300 MHz or more), and the ADC sample width can be wider than what the built-in Virtex-5 ISERDES_NODELAY primitives officially support (12 bits or more). The Virtex-5 User Guide does not specify how to configure the ISERDES_NODELAY primitives for such higher bit-widths.

A new SystemVerilog design was written that is simpler and uses fewer hardware resources than the reference design described in Xilinx Application Note XAPP866. It has been shown to work in a Xilinx XC5VSX24OT connected to a MAXIM MAX1438 12-bit ADC using a 50-MHz sample clock. The design can be replicated in the FPGA for multiple ADCs (four instantiations were used for a total of 28 channels).

This work was done by Gregory H. Taylor of Caltech for NASA’s Jet Propulsion Laboratory.

The software used in this innovation is available for commercial licensing. Please contact Daniel Broderick of the California Institute of Technology at This email address is being protected from spambots. You need JavaScript enabled to view it.. NPO-48191

This Brief includes a Technical Support Package (TSP).
High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA

(reference NPO-48191) is currently available for download from the TSP library.

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This article first appeared in the February, 2012 issue of NASA Tech Briefs Magazine.

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