A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multiapplication acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems.

FPGA chips can be responsive to realtime demands for changing applications’ needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

This work was done by Aravind Dasu and Robert Barnes of Utah State University Research for Goddard Space Flight Center. For further information, contact the Goddard Innovative Partnerships Office at (301) 286- 5810. GSC-16303-1


NASA Tech Briefs Magazine

This article first appeared in the July, 2012 issue of NASA Tech Briefs Magazine.

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