On-Chip Power-Combining for High-Power Schottky Diode- Based Frequency Multipliers

NASA’s Jet Propulsion Laboratory, Pasadena, California

A 1.6-THz power-combined Schottky frequency tripler was designed to handle approximately 30 mW input power. The design of Schottky-based triplers at this frequency range is mainly constrained by the shrinkage of the waveguide dimensions with frequency and the minimum diode mesa sizes, which limits the maximum number of diodes that can be placed on the chip to no more than two. Hence, multiple-chip power-combined schemes become necessary to increase the power-handling capabilities of high-frequency multipliers. However, the traditional powercombining topologies that are used below 1 THz present some inconvenience beyond 1 THz. The use of Y-junctions or hybrid couplers to divide/combine the input/output power at these frequency bands increases unnecessarily the electrical path of the signal in the range of frequencies where waveguide losses are considerable. Also, guaranteeing a perfect alignment of the very small chips during assembly, in order to preserve the balanced nature of the multiplier, is practically impossible with the subsequent impact on the multiplier performance.

The design presented here overcomes these difficulties by performing the power-combining directly on-chip. Four E-probes are located at a single input waveguide in order to equally pump four mulitplying structures (featuring two diodes each). The produced output power is then recombined at the output using the same concept. The four multiplying structures are physically connected on one chip, so that the alignment and symmetry of the circuits can be very well preserved. Contrary to traditional frequency triplers, in this design the input and output waveguides are perpendicular to the waveguide channels where the diodes are located. Therefore, the multiplier block is easier to fabricate with silicon micromachining technology instead of regular machining. The expected conversion efficiency of the tripler is ≅2 to 3% over a ≅20% bandwidth, which is similar to that which is simulated for an equivalent single-chip tripler driven with one fourth the input power.

This work was done by Goutam Chattopadhyay, Imran Mehdi, Erich T. Schlecht, and Choonsup Lee of NASA’s Jet Propulsion Laboratory and Caltech; Jose V. Siles – Fulbright Fellow at NASA’s Jet Propulsion Laboratory; Alain E. Maestrini of the University of Paris; Bertrand Thomas of Radiometer Physics; and Cecile D. Jung of ORU for NASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
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NPO-48155

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