As small gasoline engines evolve to use more sophisticated electronic engine controls, new challenges will face the smallengine manufacturers, including constraints in size and cost, as well as having to meet new emission and fuel efficiency standards driven by recent legislation. The rapid miniaturization of electronic components, as a side benefit of the smartphone and tablet market explosion, will help manufacturers meet these challenges, but new system and circuit topologies will also be required.

An example of stacked and SiP Multiple-Chip Modules (MCMs).
One of these new topologies is the Multiple Chip Module (MCM). Integration of analog circuits and microcomputers into a single SiP (System in Package) MCM can be a benefit. For small gasoline engine control, additional functionality and performance enhancements can be obtained through the use of software algorithms and calibration tables that are not possible with older mechanical fixed timing architectures. The MCM approach reduces the size and cost of engine controllers while increasing the reliability over discrete component solutions. A single micro-programmable MCM can replace dozens of discrete components and increase design reusability.

Two reference design engine control units were produced — one using discrete components and the other using the new SiP MCM architecture. To reduce the cost and size of a small-engine ECU (Engine Control Unit), the number of components and/or the size of these components used must be reduced. Reducing the total component count of an ECU is effective only to a certain point. Once all the unnecessary components are identified and removed, there is usually no additional way to reduce cost except by innovative circuit design or the additional integration of discrete circuit components into a custom or semi-custom integrated circuit (IC). Since the singlechip ECU is currently not possible, the next best alternative is to place two silicon chips in one package. This achieves the goal of the single package space reduction and cost reduction, but with the advantage of using currently available semiconductor technology.

There are two ways to physically collocate two silicon chips into a single molded package MCM: side-by-side or stacked one on top of the other. The side-by-side MCM is the SiP approach, and the one chip on top of another approach is the stacked approach (see figure).

In the stacked chip approach, one chip is attached to the package lead frame first. The pads on this chip are then wire bonded to the appropriate lead frame bonding pins. Depending on the size of the second chip to be stacked, it may be necessary to add a spacer chip to the top surface of the first chip to prevent the first chip's wire bond bends from touching the bottom of the second chip. Next, the spacer chip or the second chip is attached to the top of the first. Once the stack is complete, the pads on the top chip are then wire bonded to the remaining lead frame bonding pins or between the two chips for interchip bonding. In the stacked chip approach, consideration must be given to the total stacked chip height.

In the SiP approach, two chips are arranged side-by-side, and both chips are physically attached to the lead frame using normal die attachment techniques. There is no need to thin the chips, nor is there any need for a separate spacer chip. If the SiP is created using chips that have already been designed to be used in a standalone packages, then it may be difficult to bond out every pad from the side of each chip that faces the other chip. When a new chip is designed for use both in standalone and SiP packages, duplicate pads can be added on the three remaining sides to alleviate this problem.

In the SiP design, it is easy to reserve one side of the package for the high-current drivers and their associated power grounds, and the other side for the MCU and A/D converter inputs. With the stacked approach, where the pins of both chips are interspersed on all four sides of the package, this segregation is difficult. The SiP can be designed to allow the outputs from the MCU to be located near to the inputs on the analog chip thus allowing the PC board trace routing between the two chips to be minimized. The same applies to the outputs from the analog chip connected to the inputs on the MCU. Having both chips in a single package, whether SiP or stacked, allows for shorter PC board traces between the two chips, which can cut down on both radiated emissions and electromagnetic susceptibility.

The placement of two ICs in a single package poses an interesting problem for test engineers. If both ICs were of the same genus, digital or analog, the testing would be simple. The same automatic test equipment (ATE) could be used to test both chips. Because the small-engine SiP requires both a digital microcomputer chip and an analog interface chip, testing both chips on the same ATE is difficult. The main limitation of most of analog testers is functional pattern depth, which decides the size and number of program patterns. Digital testing for a microcomputer is beyond the capacity of an ATE designed to test analog circuits.

The need to convert small-engine control systems from mechanical to electronic control is a given. Small-engine manufacturers cannot meet the new emission and efficiency requirements mandated by local governments without using electronic controls. The solution to adding these controls to small engines is to reduce the size and cost of the ECU.

New techniques of reducing electronic component counts include using ASICs and ASSPs to integrate functions into a single chip, and the use of MCMs to reduce the number of packages. Using a SiP MCM as opposed to a stacked MCM will increase the reliability of an analog/MCU MCM, and will result in lower system cost and improved manufacturability.

This work was done by Ralph Ferrara of Freescale Semiconductor. The full technical paper on this technology is available for purchase through SAE International at http://papers.sae.org/2012-32-0046/ .


NASA Tech Briefs Magazine

This article first appeared in the December, 2013 issue of NASA Tech Briefs Magazine.

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