Wafer-level integration was employed to mount the microshutter array for the James Webb Space Telescope (JWST) and the detector-read-out hybrid for TIRS (Thermal Infrared Sensor). In the case of the JWST substrate, two conductors (polysilicon and aluminum) separated by a silicon oxide insulating layer were fabricated on a roughly 85-mm-square silicon wafer. The size of the substrate, the density and length of the conductive traces, and the requirement of zero shorts and zero opens on the finished device necessitated nearly impossible cleanroom requirements. Techniques were developed to repair the inevitable shorts and opens created during the wafer fabrication process. The wafers were repaired to zero shorts and zero opens without degradation of device performance.

Certain types of shorts and opens can be repaired by simply stripping and re-patterning the wafer, but there is no guarantee that the same defect will not occur again at the same or a new location. Shorts under a conductive trace cannot be repaired by simply re-patterning. Laser ablation can be used to repair certain shorts, but there is no guarantee that the repair will be successful.

The wafer is coated with photoresist of a suitable thickness to protect the wafer — typically 1 to 3 μm. The area to be repaired is observed under a microscope with a filter to block ultraviolet and short wavelength visible light to prevent exposure of the photoresist. Using an adjustable iris and changing microscope objective (if necessary), the area is exposed to the full spectrum of the microscope light by removing the optical filter for a suitable period of time — typically one second to 200 seconds. Multiple areas can be exposed in the same manner. After all areas are exposed, the wafer is developed as normal. The exposed area of the wafer is now ready for subsequent processing either deposition of a conductive layer or wet or dry etching.

This work was done by Larry Hess and David Franz of Goddard Space Flight Center. For further information, contact the Goddard Technology Transfer Office at (301) 286-5810. GSC-16403-1


NASA Tech Briefs Magazine

This article first appeared in the October, 2014 issue of NASA Tech Briefs Magazine.

Read more articles from this issue here.

Read more articles from the archives here.