A concept was developed for a multi-gigabit-rate, radiation-hardened (RH) bus that would support open-system architecture and provide a cost-effective, high-speed interconnect. This concept is based on Advanced Science and Novel Technology Company’s SerDes system, which supports a variety of interfaces, and operates at frequencies from DC to more than 15 GHz. The design of the improved SerDes is based on the company’s proprietary library of RH cells and functional blocks using annular FETs (field-effect transistors) that are available in commercial CMOS (complementary metal-oxide-semiconductor) technologies. Bus architecture and preliminary SerDes circuit design have been accomplished during this phase. At the time of this reporting, the complete chip was to be designed and fabricated in the next phase.
The proposed SerDes is expected to convert 3-Gb/s serial data streams into 150-Mbs parallel signals, and back. It can be understood that implementation of 150-Mb/s circuitry in high-speed SiGe technology is unreasonable. A more suitable design approach is associated with CMOS architectures that also allow for supply voltages below 2 V. At the same time, achievement of the desired radiation tolerance requires application of annular transistor structures that significantly affects the circuit speed performance. The company’s investigations show that 130-nm annular transistors can reliably operate up to 1.5 to 2.0 GHz, while 90-nm transistors can achieve 4.0 to 4.5 GHz. Based on this, it has been decided to use the IBM’s 9SF CMOS technology for the implementation of the MARUS SerDes chip.
This work was done by Vladimir Katzman of Advanced Science and Novel Technology Company for Goddard Space Flight Center. For further information, contact the Goddard Technology Transfer Office at (301) 286-5810. GSC-16366-1