Improved optoelectronic pattern recognition encoders that measure rotary and linear 1-dimensional positions at conversion rates (numbers of readings per unit time) exceeding 20 kHz have been invented. Heretofore, optoelectronic pattern-recognition absolute-position encoders have been limited to conversion rates <15 Hz — too low for emerging industrial applications in which conversion rates ranging from 1 kHz to as much as 100 kHz are required. The high conversion rates of the improved encoders are made possible, in part, by use of vertically compressible or binnable (as described below) scale patterns in combination with modified readout sequences of the image sensors [charge-coupled devices (CCDs)] used to read the scale patterns. The modified readout sequences and the processing of the images thus read out are amenable to implementation by use of modern, high-speed, ultra-compact microprocessors and digital signal processors or field-programmable gate arrays. This combination of improvements makes it possible to greatly increase conversion rates through substantial reductions in all three components of conversion time: exposure time, image-readout time, and image-processing time.
In a typical prior optoelectronic pattern- recognition absolute-position encoder, the CCD is oriented with its horizontal axis parallel to the axis along which the position of the scale pattern is to be measured. The pattern includes vertically oriented fiducial bars plus small rectangles or squares, representing code bits, that serve to uniquely identify the fiducial bars (see Figure 1). The lower limit on conversion time is determined primarily by the exposure time and the time required to read out the entire image from the CCD, pixel by pixel. The exposure time must be long enough to obtain adequate signal-tonoise ratios in the code-bit marks. The requirement for pixel-by-pixel readout of the entire image arises from the use of vertical (as well as horizontal) position information to distinguish among code-bit marks in different rows.
In conventional pixel-by-pixel readout, during each row-readout clock cycle, the signal contents of all the pixels of each row are shifted down to the next row, except that the contents of the bottom row are shifted down to a serial register, which triggers analog-to-digital conversion of each pixel’s signal. Then, before the beginning of the next row-readout clock cycle, the contents of the serial register are shifted out, one pixel at a time, in response to sequence of column-readout pulses.
In vertically binned readout, which is an established alternative to conventional pixel-by-pixel readout, the sequence of clock pulses is modified so that the contents of multiple rows are shifted down to the serial register before applying the column-readout pulses. As a result, vertical resolution is lost, but time needed for reading out the image charge from all the pixels is reduced by a factor equal to the number of rows shifted prior to shifting the column contents out of the serial register. Moreover, the image-data processes needed to extract the vertical spatial information to determine row locations of code-bit marks can be eliminated. Inasmuch as the consequent loss of vertical resolution does not adversely affect the desired measurement of horizontal position, vertical binning can thus be used to reduce readout time substantially, provided that the scale pattern is such that the horizontal spatial information in the code-bit marks suffices to uniquely identify the fiducial bars. A scale pattern that satisfies this requirement is said to be vertically binnable.
Figure 2 shows an example of a vertically binnable scale pattern. The vertical stripes spanning the entire field from top to bottom are the fiducial bars. The stripes that extend part way up from the bottom and part way down from the top are the code-bit marks. The code-bit marks at the top and bottom are identical, so that the image can be binned by the full height (that is, all the rows can be included in the bin for each column, enabling maximum speedup). Other patterns in which code bits at top and bottom differ but identify a greater number of fiducials dramatically increase range, while still greatly speeding up readout. Among the secondary advantages of such a vertically binnable pattern is that the vertical alignment of the CCD relative to the pattern is much less critical than is the alignment needed to utilize the vertical spatial information in a conventional pattern with pixel-by-pixel readout.
This work was done by Douglas B. Leviton of Goddard Space Flight Center. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/ Computers category.
This invention is owned by NASA, and a patent application has been filed. Inquiries concerning nonexclusive or exclusive license for its commercial development should be addressed to
the Patent Counsel
Goddard Space Flight Center
Refer to GSC-14633-1.