High-temperature electronic integrated circuits have been demonstrated in silicon carbide (SiC) depletion mode MESFETs. This process is only capable of producing depletion mode n-channel MESFET transistors. With only this type of transistor, designing a logic gate is a challenge. A previous logic gate design that can be constructed in the current process has performed well. This invention improves upon the previous design by increasing output voltage range and decreasing the physical layout size of a logic gate. This logic gate circuit consists of depletion mode MESFET/JFET transistors and resistors that can be constructed with SiC depletion mode n-channel MESFETs.

The circuit is comprised of three circuit constructs: a current source (Q1 and Rs) consisting of one transistor and one resistor, a current steering switch input stage (Q2) consisting of at least one transistor, and a resistor divider level shifting output stage (R1 and R2). The current source comprised of Q1 and Rs provides current to bias the output stage, and limits the total device current in the logic gate. The current steering input stage of Q2 steers current to set the output stage bias point, depending on input logic signal state.

Finally, the resistor divider level shifting output stage sets the output stage bias points and further develops valid output logic signal states. The circuit has two operating points: logic high input and logic low input. As the basis gate for logic functions, the simplest function performed by the gate is the inverting or NOT function, which results in a logic high output for a logic low input, and a logic low output for logic high input. As an inverting logic gate, and treating the current steering input stage transistor as a switch, the circuit will have two ideal operating points. These ideal operating points illustrate optimal circuit operation; realized circuit operating points will differ from the ideal cases, but operation is similar. The logic level high refers to 0V, and the logic level low refers to a negative voltage equal to 1/2Vss. Replacing Q2 with series and/or parallel transistor networks results in more complex logic constructs such as NOT AND (NAND), NOT OR (NOR), and in combination, complex sum of product functions.

This work was done by Michael Krasowski and Norman Prokop of Glenn Research Center. NASA invites and encourages companies to inquire about partnering opportunities. NASA is seeking partners to further develop this technology through joint cooperative research and development. For more information about this technology and to explore opportunities, please contact This email address is being protected from spambots. You need JavaScript enabled to view it.. LEW-19356-1

NASA Tech Briefs Magazine

This article first appeared in the June, 2016 issue of NASA Tech Briefs Magazine.

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