Electronic devices are getting smaller and more energy-efficient, meaning that they are more susceptible to single event upsets (SEUs) — malfunctions caused by particles in the atmosphere interfering with electronic systems. The need increases as these devices get smaller, since particles that cause these upsets can even come from the packages that house the devices. This is especially prevalent in the aerospace industry, since working at higher altitudes means increased exposure to cosmic ray particles.
There are two widely used SEU hardening techniques: tech hardening and design hardening. Tech hardening involves making changes to the fabrication of the chip to reduce SEU occurrences. These fabrication processes can cost billions of dollars to develop.
The Single Event Upset Suppression System (SEUSS) is a latch that suppresses these single event upsets. SEUSS gives electrical engineers freedom of design, since it can behave like any known latch (SR latch, D latch, T flip flop, JK flip flop, etc.). It offers single event upset tolerance while maintaining flexibility in design, and saves money in the process.
SEUSS cells are designed to be immune to SEUs. CMOS transistors are configured to operate as a SEU-tolerant SR latch. The SEUSS cells come in two different variations. One version emulates a cross-coupled NOR gate SR flip-flop (SEUSSNor); the other emulates a cross-coupled NAND gate SR flip-flop (SEUSSNand). This flexible device, when configured as a SEU-tolerant SR latch, can be converted into any known type of latch.
One benefit of the SEUSS latch is that it can be fabricated in any modern integrated circuit process that provides complementary transistors. Another benefit is that scaling is not required to make the design functional. The SEU tolerance of the invention is not affected by any external logic that may be added.
The SEUSS technology can be set or reset either synchronously or asynchronously; therefore, redundant circuitry can be added to the invention to increase its SEU tolerance.