Compact, highly customizable digital receivers are being developed for the system described in "Radar Interferometer for Topographic Mapping of Glaciers and Ice Sheets" (NPO-43962), NASA Tech Briefs, Vol. 31, No. 7 (August 2007), page 72. In the original intended application, there is a requirement for 16 such receivers, each dedicated to, and mounted directly on, one antenna element in a 16-element array. The receivers are required to operate in unison, sampling radar returns received by the antenna elements in a digital beam-forming (DBF) mode. The design of these receivers could also be adapted to commercial radar systems. At the time of reporting the information for this article, there were no commercially available digital receivers capable of satisfying all of the operational requirements and compact enough to be mounted directly on the antenna elements.
The figure depicts the overall system of which the digital receivers are parts. Each digital receiver includes an analog-to- digital converter (ADC), a demultiplexer (DMUX), and a field- programmable gate array (FPGA). The ADC effects 10-bit band-pass sampling of input signals having frequencies up to 3.5 GHz. (In the original intended application, the input signals would be intermediate- frequency signals obtained through down-conversion of signals from a radio frequency of several tens of gigahertz.) The input samples are demultiplexed at a user-selectable rate of 1:2 or 1:4, then buffered in part of the FPGA that functions as a first-in/first-out (FIFO) memory. Another part of the FPGA serves as a controller for the ADC, DMUX, and FIFO memory and as an interface between (1) the rest of the receiver and (2) a front-panel data port (FPDP) bus, which is an industry-standard parallel data bus that has a high-data- rate capability and multichannel configuration suitable for DBF.
Still other parts of the FPGA in each receiver perform signal-processing functions. The design exploits the capability of FPGAs to perform high-speed processing and their amenability to customization. There is ample space available within the FPGA to customize it to implement such application- specific, real-time processes as digital filtering and data compression. To afford additional operational flexibility and to enable use of a receiver in other applications, the design also includes a provision for an additional "drop-in" circuit board containing analog amplification and filtering circuitry. Such boards, which are relatively simple and inexpensive, can be easily exchanged by the user to modify center-frequency, bandwidth, and signal-level parameters.
The digital receivers can be configured to operate in a stand-alone mode, or in a multichannel mode as needed for DBF. In the multichannel/DBF mode, the re ceivers are made to take turns in transmitting sampled data onto the bus. The bus port on each receiver adheres to the FPDP-II standard, which supports an aggregate data rate of 400 MB/s. While the primary role of the FPDP bus is to transmit sampled data from receivers to a data-storage unit, the bus can also be used to transmit configuration data to the receivers. The bus also enables the receivers to communicate with one another — a capability that could be useful in some applications. Each receiver is also equipped with an RS-232 interface, through which configuration data can be communicated.
The data on the bus are aggregated and then sent to a data-acquisition (DAQ) subsystem by means of a serial FPDP interface that, like each receiver, contains an FPGA that serves partly as a FIFO memory and partly as a control unit. The DAQ subsystem stores the data onto a hard-disk array for postprocessing. In its role as a control unit, this FPGA sends timing and configuration information to each of the 16 receivers.
Although band-pass sampling is a widely applied technique, heretofore, it has been little used in radar systems. The use of band-bass sampling in the present receiver design is what makes it possible to achieve compactness: Band-pass sampling makes it possible to feed, as input to the ADC, signals having higher frequencies than could otherwise be utilized. In so doing, band-pass sampling enables elimination of an additional down-conversion stage that would otherwise be needed, thereby reducing the design size of the receiver. This design approach also eases filtering constraints and, in so doing, reduces the required sizes of filters.
The customizability of the receiver makes it applicable to a broad range of system architectures. The capability for operation of receivers in either a stand-alone or a DBF mode enables the use of the receivers in an unprecedentedly wide variety of radar systems.