A “smart” back-gate driver circuit has been proposed to enable the operation, at voltages higher than were previously possible, of a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated circuit that contains both low- and high-voltage transistors energized by corresponding low- and high-voltage power supplies. As used here, “low voltage” signifies potentials ≤3.3 V, while “high voltage” signifies potentials ≥40 V. The purpose of the back-gate driver circuit is to raise the threshold (turn-on) voltages of parasitic back-channel transistors (BCTs) that unavoidably exist in such an integrated circuit (see Figure 1). Turn-on of the parasitic transistors is unacceptable because it causes short circuits that render the integrated circuit inoperative.
In a mixed-voltage (high-voltage/low-voltage) SOI CMOS integrated circuit, the turn-on threshold voltages of parasitic BCTs are usually less than the voltage that the high-voltage transistors can withstand; heretofore, this fact has made it necessary to limit voltage ratings accordingly. The problem is complicated by the fact that ionizing radiation causes the accumulation of positive charges in the buried oxide layer of the integrated circuit, and these charges lower the threshold voltages of the parasitic BCT.
The proposed back-gate driver circuit would apply, to the integrated-circuit substrate, a bias voltage that would ensure that the parasitic BCTs remain in the “off” state at voltages beyond those that would otherwise cause the parasitic transistors to turn on. The proposed back-gate driver circuit is characterized as “smart” because it would sense the effect of ionizing radiation on the threshold voltages and would respond by adjusting the bias voltage that it applies so as to maximize the margin of turn-off of the parasitic transistors.
Figure 2 is a simplified schematic diagram of the proposed circuit. A current of 1 µA would be forced through one ntype back-channel transistor (BCT). The source of this BCT would be biased to –5 V to ensure that its gate-to-source voltage (VGS) was 5 V greater than that of any other n-type BCT on the integrated- circuit chip. Feedback would force this VGS to a level that would cause a current of 1 µA to flow in this one BCT. This VGS would slightly exceed the turn-on voltage of this BCT, forcing the substrate voltage to be approximately 5 V less than the turn-on voltages of all other n-channel BCTs on the chip. Exposure of the integrated circuit to aging would cause the turn-on voltages of the both the p- and n-type BCTs to shift in the same direction by about the same amount. Thus, by shifting the substrate- bias voltage in response to the sensed turn-on of one n-type BCT, the proposed circuit would maintain voltage margins against turn-on of both the remaining n-type BCTs and all the ptype BCTs.
This work was done by Mohammad Mojarradi of Caltech, Benjamin Blalock of Mississippi State University, and Harry Li of the University of Idaho for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech. com/tsp under the Electronic Components and Systems category. NPO-20910
This Brief includes a Technical Support Package (TSP).
Unfortunately the TSP Enabling Higher-Voltage Operation of SOI CMOS Transistors (reference NPO-20910) appears to be missing from our system.
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