An integrated circuit (IC) physical layout has been developed for the HCD ASIC - an application-specific integrated circuit that decodes digital command signals transmitted from a ground station to a spacecraft (uplink commands). The HCD ASIC is described in "Hardware-Command-Decoding ASIC" (NPO-19615), which appears elsewhere in this issue of NASA Tech Briefs. The present physical layout will be converted to a mask for IC fabrication of the HCD ASIC.

The physical layout has been extensively simulated for its functions of receiving and decoding the uplink commands through a programmable read-only memory (PROM) interface, including conversion of the command data from the serial uplink format to parallel format. At the same time, the HCD ASIC provides detection of some triple bit errors, detection of all double bit errors, and correction of all single-bit errors in the uplink commands, plus detection of hardware faults, all at unprecedented speed. Another unique feature is the use of the double-buffer method for read/write and status for resolving overruns.

This work was done by Gary S. Bolotin, James A. Donaldson, Huy H. Luong, and Steven H. Wood of Caltech for NASA's Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

Technology Reporting Office
JPL
Mail Stop 122-116
4800 Oak Grove Drive
Pasadena, CA 91109
(818) 354-2240

Refer to NPO-19628


This Brief includes a Technical Support Package (TSP).
ASIC physical layout for the HCD ASIC

(reference NPO19628) is currently available for download from the TSP library.

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NASA Tech Briefs Magazine

This article first appeared in the June, 1998 issue of NASA Tech Briefs Magazine.

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