A program to demonstrate the feasibility of GaAs-based Kₐ -band power amplifiers has generated a number of technological advances. The goals of the program included (1) capability of amplifier operation at center frequencies of 23, 29, and 32.5 GHz; (2) bandwidth of 5 percent at each center frequency; and (3) gains and output power levels as specified in the table. Each amplifier was to contain three metal/semiconductor field-effect transistor (MESFET) stages, the MESFET gate width in each stage being larger than that of the preceding stage (see figure). During the program, one- and two-stage amplifier submodules with various input and output network configurations were also constructed and tested to characterize the input, output, and interstage-matching electrical characteristics of the networks.

At the beginning of the program, odd-shaped vapor-phase epitaxial (VPE) MESFET wafers were used. A breakthrough in power and efficiency was achieved by use of highly doped (doping density 8 × 1017cm¯3) MESFET material grown by molecular-beam epitaxy. At an operating frequency of 34 GHz, a monolithic amplifier that had gate widths of 50, 100, and 250 µm exhibited a gain of 16 dB, yielding an output power of 112 mW with 21.6-percent efficiency.

The Parameters in the Table represent the amplifier-performance goals at various stages of the program.

The next breakthrough came with the use of heterostructures grown by MBE (AlGaAs/InGaAs wherein the InGaAs was highly doped). These heterostructures made it possible to achieve high power density with high efficiency. For example, a single-stage monolithic microwave integrated circuit (MMIC) amplifier containing a MESFET with gate width of 100 ?m exhibited an efficiency of 40 percent at 32.5 GHz. The corresponding three-stage amplifier (with gate widths of 50, 100, and 250 µm) put out 180 mW at a gain of 23 dB and an efficiency of 30.3 percent.

These Block Diagrams depict the basic performance requirements for the amplifier stages. The dimension below each symbol is the MESFET gate width, the decibel number inside each amplifier symbol represents the nominal stage gain, and the other decibel numbers denote nominal power levels at the indicated locations.

The next breakthrough was achieved with 3-in. (7.6-cm) pseudomorphic high-electron-mobility transistor (PHEMT) wafers, each incorporating an etch-stop layer for the gate recess (made by reactive-ion etching). Again, state-of-the-art performances were achieved: efficiency of 40 percent with output power of 235 mW and gain of 20.7 dB. A single-stage 2 × 600-µm chip generated an output power of 794 mW with a gain of 5 dB and a power-added efficiency of 38.2 percent.

This work was done by Edward J. Haugland of Lewis Research Center and Paul Saunier and Hua Quen Tserng of Texas Instruments, Inc.

Inquiries concerning rights for the commercial use of this invention should be addressed to

NASA Lewis Research Center
Commercial Technology Office
Attn: Tech Brief Patent Status
Mail Stop 7-3
21000 Brookpark Road
Cleveland
Ohio 44135

Refer to LEW-16626.


NASA Tech Briefs Magazine

This article first appeared in the October, 1998 issue of NASA Tech Briefs Magazine.

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