A high-rate digital receiver (HRDR) implemented as a peripheral component interface (PCI) board has been developed as a prototype of compact, general- purpose, inexpensive, potentially mass-producible data-acquisition interfaces between telemetry systems and personal computers. The installation of this board in a personal computer together with an analog preprocessor enables the computer to function as a versatile, highrate telemetry-data-acquisition and demodulator system. The prototype HRDR PCI board can handle data at rates as high as 600 megabits per second, in a variety of telemetry formats, transmitted by diverse phase-modulation schemes that include binary phase-shift keying and various forms of quadrature phaseshift keying. Costing less than $25,000 (as of year 2003), the prototype HRDR PCI board supplants multiple racks of older equipment that, when new, cost over $500,000. Just as the development of standard network-interface chips has contributed to the proliferation of networked computers, it is anticipated that the development of standard chips based on the HRDR could contribute to reductions in size and cost and increases in performance of telemetry systems.

The circuitry on the HRDR board includes an analog-to-digital converter (ADC) and two high-rate digital demodulator (HRDD) application-specific integrated circuits (ASICs). The HRDR board accepts a baseband radio frequency telemetry modulation signal as input. The ADC ASIC samples the input, and the sampled data is demultiplexed and sent to the two HRDD ASICs, which demodulate the signal, recover the clock and data components of the modulation, bit-synchronize the data, and serialize and forward the data to the next stage. In addition, the HRDD ASICs remove Doppler shifts from the carrier and data signals. Within each HRDD ASIC, the data are further demultiplexed by a factor of two so that the HRDD processing takes place in a total of four streams— each stream at a quarter of the incomingdata rate. Processing in multiple streams at a rate lower than the incoming-data rate makes it possible to use complementary metal oxide/semiconductor processing circuitry that is relatively inexpensive and could not perform adequately at the incoming-data rate.

The HRDR board outputs, depending on output interface setup, one or two synchronous differential emitter coupled logic (ECL) clock and data output streams. The output interface can be programmed to process and output demodulated telemetry data in multiple ways — for example, to perform CCSDS standard Viterbi decoding of convolutionally encoded data using either 3 bit soft symbols or hard symbols as inputs, interleave data I and Q channels into a single output stream, or to output each channel independently. The user can easily choose the output format by means of a simple graphical user interface.

This work was done by Parminder Ghuman, Thomas Bialas, and Clifford Brambora of Goddard Space Flight Center and David Fisher of QSS Group, Inc. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/Computers category. GSC-14780-1


NASA Tech Briefs Magazine

This article first appeared in the December, 2004 issue of NASA Tech Briefs Magazine.

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