A document discusses placing memory modules on the high-speed serial interconnect, which is used by a spacecraft’s computer elements for inter-processor communications, to allow all multiple computer system architectures to access the spacecraft data storage at the same time. Each memory board is identical electrically and receives its bus ID upon connection to the system. The computer elements are configured in a similar fashion. The architecture allows for multiple memory boards to be accessed simultaneously by different computer elements, and results in a scalable, strong, fault-tolerant system. The IEEE-1393 ring bus can be routed so that multiple card failures can occur and the mass memory storage will still function.

This work was done by Brian Cox of Caltech for NASA’s Jet Propulsion Laboratory.


This Brief includes a Technical Support Package (TSP).
Network-Attached Solid-State Recorder Architecture

(reference NPO-45204) is currently available for download from the TSP library.

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This article first appeared in the November, 2008 issue of NASA Tech Briefs Magazine.

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