A report discusses integrating multiple memory modules on the high-speed serial interconnect (IEEE 1393) that is used by a spacecraft’s inter-module communications in order to ease data congestion and provide for a scalable, strong, flexible system that can meet new system-level mass memory requirements.

Using the JPL 1393 Ring Bus Interconnect to link computer elements, I/O, and memory allows any element to communicate with any other element. Besides providing a consistent approach to exchanging data, it inherently has a layer of abstraction that allows for better system and software design. This new architecture is fault-tolerant and provides a large range of scalability while supporting flexible spacecraft architectures that are currently being investigated.

This work was done by Brian Cox, Jeffrey Mellstrom, and Terry Wysocky of Caltech for NASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management

JPL

Mail Stop 202-233

4800 Oak Grove Drive

Pasadena, CA 91109-8099

E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

Refer to NPO-45205, volume and number of this NASA Tech Briefs issue, and the page number.


This Brief includes a Technical Support Package (TSP).
System-Level Integration of Mass Memory

(reference NPO-45205) is currently available for download from the TSP library.

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This article first appeared in the November, 2008 issue of NASA Tech Briefs Magazine.

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