For complex boards with multiple FPGAs, each FPGA can implement its own remote terminal (RT) core and present itself logically to the bus as a remote terminal while sharing the RT’s hardware. This simplifies the design since commands and telemetry do not have to be distributed and collected by user logic; instead, the MIL-STD-1553B protocol does the work. Thus, the designer is more efficient, the system is simpler, and often the system is smaller and lower power.
The incoming MIL-STD-1553B signals are distributed or relayed to each RT protocol engine. This complies with MIL-STD-1553B since each RT is required to see and process each command from the BC.
The outgoing MIL-STD-1553B signals are generated by one spot in the logic. This “spot” is the output of a simple multiplexor that steers the active transmitting RTs signals to the MIL-STD-1553B bus. This complies with MIL-STD-1553B specification since there can only be one transmitter on the bus at a time. Broadcast commands do not result in multiple RTs responding with status words; thus, there are no collisions.
One implementation uses the RT protocol’s TX_INH signal to switch the mux to the transmitting RT protocol engine. Care must be taken when a reprogrammable FPGA is one of the RTs to ensure that “garbage” signals are not placed on the MIL-STD-1553B bus prior to the device’s being properly configured and started.
The major expense of a MIL-STD-1553B RT is the power, mass, volume, and expense of the transceivers, transformers, and connectors. These can be shared by multiple RTs on the same card or in the same box. The MIL-STD-1553B protocol can save design time and logic by distributing commands to each RT as well as time-sharing the real bus for the virtual RTs. This greatly simplifies the designer’s job in many cases, which makes the system more reliable and more easily and thoroughly tested.