In a proposed coding-and-modulation scheme, a high-rate binary data stream would be processed as follows:

  1. The input bit stream would be demultiplexed into multiple bit streams.
  2. The multiple bit streams would be processed simultaneously into a high-rate outer Hamming code that would comprise multiple short constituent Hamming codes — a distinct constituent Hamming code for each stream.
  3. The streams would be interleaved. The interleaver would have a block structure that would facilitate parallelization for high-speed decoding.
  4. The interleaved streams would be further processed simultaneously into an inner two-state, rate-1 accumulator code that would comprise multiple constituent accumulator codes — a distinct accumulator code for each stream.
  5. The resulting bit streams would be mapped into symbols to be transmitted by use of a higher-order modulation — for example, M-ary phase-shift keying (MPSK) or quadrature amplitude modulation (QAM).

The Encoder and Decoder would concatenate and interleave an outer set of parallel constituent Hamming codes with an inner set of parallel constituent accumulator codes.
The novelty of the scheme lies in the concatenation of the multiple-constituent Hamming and accumulator codes and the corresponding parallel architectures of the encoder and decoder circuitry (see figure) needed to process the multiple bit streams simultaneously. As in the cases of other parallel-processing schemes, one advantage of this scheme is that the overall data rate could be much greater than the data rate of each encoder and decoder stream and, hence, the encoder and decoder could handle data at an overall rate beyond the capability of the individual encoder and decoder circuits. A less-obvious advantage is that the scheme would utilize bandwidth efficiently and would make it possible to reduce transmitter power by about 2 dB without exceeding a given bit-error rate for the best prior coding-and-modulation scheme.

In one instantiation of the scheme, the outer code would consist of 372 Hamming codes characterized by a block length of 15 symbols, of which 11 would be information symbols [denoted a (15,11) code in the art]. The inner code would consist of 15 rate-1, two-state accumulator codes of block length 372. The parallel nature of the interleaver would enable the permutation of the 15 symbols of each of the 372 Hamming code words by 372 independent interleavers, and the 15 groups of 372 Hamming symbols would be permuted by 15 independent interleavers before being fed to the 15 accumulators. This code structure at the transmitter would enable the use, in the receiver, of a high-speed iterative decoder that could include 372 soft-input, soft-output (SISO) modules to decode the 372 constituent Hamming codes in parallel and 15 SISO modules to decode the 15 constituent accumulator codes in parallel. Hence, the overall decoder could have a parallel architecture.

This work was done by Dariush Divsalar and Samuel Dolinar of Caltech for NASA’s Jet Propulsion Laboratory. For further information, contact This email address is being protected from spambots. You need JavaScript enabled to view it.. NPO-40678


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This article first appeared in the March, 2009 issue of NASA Tech Briefs Magazine.

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