Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G4FETs and described below. These logic circuits are intended to serve as prototypes of more- complex advanced programmable-logic-device- type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G4FETs is such that fewer discrete components are needed to perform a given logic function in G4FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G4FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in “G4FETs as Universal and Programmable Logic Gates” (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44.
The real-time-reconfigurable logic gate can be realized, in a circuit partly resembling the adjustable-threshold inverter, by applying the logic input signals to JG1 and JG2 and connecting the input terminal of what would otherwise be the inverter to a constant reference voltage (that is, making Vin a constant voltage). The number of transistors in this circuit is smaller than in a classical CMOS circuit that performs an equivalent logic function. The same hardware can be made to form any of three different functions: Depending on the value of Vin, the function is disabled output (Vout = VDD or 0), the NOR of the logic levels represented by VJG1 and VJG2, or the NAND of the logic levels represented by VJG1 and VJG2.
In the DRAM cell, the lateral inversion-mode PMOSFET (a MOSFET having a p-doped channel and an n-doped Si substrate) inherent in the n-channel G4FET is used for writing data in the horizontal direction, while the p-channel JFET serves to read the data in the vertical direction. When the WWL signal turns on the PMOS switch, the potential of the storage node (SN) is modulated by WBL. When writing is disabled, SN is isolated, and during the retention time, its depletion region is more or less extended toward the body, depending on value of the datum stored in it. As a result, the resistance of the JFET channel in the vertical direction is affected, causing the sensing current (Isense) to be a function of the stored data. The sensing-current characteristics can be optimized via the layout of the G4FET structure.
This work was done by Mohammad Mojarradi of Caltech; Kerem Akarvardar, Sorin Cristoleveanu, and Paul Gentil of Grenoble University; and Benjamin Blalock and Suhan Chen of University of Tennessee for NASA’s Jet Propulsion Laboratory.
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Refer to NPO-44007, volume and number of this NASA Tech Briefs issue, and the page number.