Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G4FETs and described below. These logic circuits are intended to serve as prototypes of more- complex advanced programmable-logic-device- type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G4FETs is such that fewer discrete components are needed to perform a given logic function in G4FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G4FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in “G4FETs as Universal and Programmable Logic Gates” (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44.

Figure 1. In a G4FET, the four gates (G1, G2, JG1, and JG2) can be biased independently. JG1 and JG2 can be considered as extra gates that provide additional degrees of freedom for design and operation, beyond those of a conventional MOSFET.
A G4FET can be characterized as an accumulation-mode silicon- on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G4FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G4FETs.

Figure 2. These G4FET Logic Circuits can be building blocks of complex programmable logic devices.
The present G4FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G4FET. The side gates (JG1 and JG2) are used to linearly modulate the threshold voltage of the G4FET, thereby modulating the switching threshold voltage of the inverter. By judiciously selecting the design and operational parameters that affect the switching threshold voltage, the inverter can be made to function as a quaternary down literal converter. (The term “down literal converter” denotes a circuit that performs a function, known as the down literal function, that is the fundamental element in multi-valued logic.) Hence, the adjustable-threshold inverter can be made a basic building block of quaternary logic circuits.

The real-time-reconfigurable logic gate can be realized, in a circuit partly resembling the adjustable-threshold inverter, by applying the logic input signals to JG1 and JG2 and connecting the input terminal of what would otherwise be the inverter to a constant reference voltage (that is, making Vin a constant voltage). The number of transistors in this circuit is smaller than in a classical CMOS circuit that performs an equivalent logic function. The same hardware can be made to form any of three different functions: Depending on the value of Vin, the function is disabled output (Vout = VDD or 0), the NOR of the logic levels represented by VJG1 and VJG2, or the NAND of the logic levels represented by VJG1 and VJG2.

In the DRAM cell, the lateral inversion-mode PMOSFET (a MOSFET having a p-doped channel and an n-doped Si substrate) inherent in the n-channel G4FET is used for writing data in the horizontal direction, while the p-channel JFET serves to read the data in the vertical direction. When the WWL signal turns on the PMOS switch, the potential of the storage node (SN) is modulated by WBL. When writing is disabled, SN is isolated, and during the retention time, its depletion region is more or less extended toward the body, depending on value of the datum stored in it. As a result, the resistance of the JFET channel in the vertical direction is affected, causing the sensing current (Isense) to be a function of the stored data. The sensing-current characteristics can be optimized via the layout of the G4FET structure.

This work was done by Mohammad Mojarradi of Caltech; Kerem Akarvardar, Sorin Cristoleveanu, and Paul Gentil of Grenoble University; and Benjamin Blalock and Suhan Chen of University of Tennessee for NASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

Refer to NPO-44007, volume and number of this NASA Tech Briefs issue, and the page number.


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