A dynamic random-access memory (DRAM) circuit that tolerates single-event upsets (SEUs) has been developed. A single-event upset is a bit flip caused by ionizing radiation. In a DRAM, the state of each bit (0 or 1) is stored as charge on a buried capacitor. The impingement of an energetic charged particle can change the charge, and thus the state of the bit. There is no way to make a DRAM completely immune to SEUs, but the probability of a bit error in the DRAM output can be reduced significantly by use of redundancy; this is the concept on which the present SEU-tolerant design is based.

For protective redundancy, the DRAM incorporates three memory cells for each single cell that would otherwise be used. During recording, a bit is written in all three cells of a triple at the same time. Upon readout, the bit from the first cell is compared with that from the second cell; if the bits from the first and second cells are equal, then one of these bits is passed on to the data processor that requested the readout. If the bits from the first and second cells are not equal (because one was changed in an SEU), then the bit from the third cell is sent to the processor.

The comparison and selection of bits to pass on to the processor are accomplished by use of comparators and bus buffers. The SEU-tolerant DRAM also contains additional signal lines for full testing and for isolation and correction of faults.

This work was done by Steven Cole of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp  under the Electronics & Computers category. NPO-20474

This Brief includes a Technical Support Package (TSP).
DRAM circuit tolerates single-event upsets

(reference NPO-20474) is currently available for download from the TSP library.

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This article first appeared in the February, 2000 issue of NASA Tech Briefs Magazine.

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